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Shift Register. CD4021BQ Datasheet

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Shift Register. CD4021BQ Datasheet






CD4021BQ Register. Datasheet pdf. Equivalent




CD4021BQ Register. Datasheet pdf. Equivalent





Part

CD4021BQ

Description

CMOS 8-Stage Static Shift Register

Manufacture

Texas Instruments

Datasheet
Download CD4021BQ Datasheet


Texas Instruments CD4021BQ

CD4021BQ; CD4021B-Q1 www.ti.com CMOS 8-STAGE STA TIC SHIFT REGISTER Check for Samples: C D4021B-Q1 SCHS378 – MARCH 2010 FEAT URES 1 • Qualified for Automotive App lications • Medium-Speed Operation: 1 2-MHz (Typ) Clock Rate at VDD – VSS = 10 V • Fully Static Operation • Ei ght Master-Slave Flip-Flops Plus Output Buffering and Control Gating • 100% Tested for Quiescent Current at .


Texas Instruments CD4021BQ

20 V • Maximum Input Current of 1 µA at 18 V Over Full Package-Temperature R ange: 100 nA at 18 V and 25°C • Nois e Margin (Full Package-Temperature Rang e): – 1 V at VDD = 5 V – 2 V at VDD = 10 V – 2.5 V at VDD = 15 V • Sta ndardized Symmetrical Output Characteri stics • 5-V, 10-V, and 15-V Parametri c Ratings • Meets All Requirements o f JEDEC Tentative Standard No. 13B, .


Texas Instruments CD4021BQ

"Standard Specifications for Description of 'B' Series CMOS Devices" • Latch- Up Performance Meets 50 mA per JESD 78, Class I APPLICATIONS • Parallel Inpu t/Serial Output Data Queuing • Parall el-to-Serial Data Conversion • Genera l-Purpose Register D PACKAGE (TOP VIEW) DESCRIPTION CD4021B series types are 8-stage parallel- or serial-input/seria l output registers having .



Part

CD4021BQ

Description

CMOS 8-Stage Static Shift Register

Manufacture

Texas Instruments

Datasheet
Download CD4021BQ Datasheet




 CD4021BQ
CD4021B-Q1
www.ti.com
CMOS 8-STAGE STATIC SHIFT REGISTER
Check for Samples: CD4021B-Q1
SCHS378 – MARCH 2010
FEATURES
1
• Qualified for Automotive Applications
• Medium-Speed Operation: 12-MHz (Typ) Clock
Rate at VDD – VSS = 10 V
• Fully Static Operation
• Eight Master-Slave Flip-Flops Plus Output
Buffering and Control Gating
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over
Full Package-Temperature Range:
100 nA at 18 V and 25°C
• Noise Margin (Full Package-Temperature
Range):
– 1 V at VDD = 5 V
– 2 V at VDD = 10 V
– 2.5 V at VDD = 15 V
• Standardized Symmetrical Output
Characteristics
• 5-V, 10-V, and 15-V Parametric Ratings
• Meets All Requirements of JEDEC Tentative
Standard No. 13B, "Standard Specifications for
Description of 'B' Series CMOS Devices"
• Latch-Up Performance Meets 50 mA per JESD
78, Class I
APPLICATIONS
• Parallel Input/Serial Output Data Queuing
• Parallel-to-Serial Data Conversion
• General-Purpose Register
D PACKAGE
(TOP VIEW)
DESCRIPTION
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each
register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q"
outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register
synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous
with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage
register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL
input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the
positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when
asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes),
16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
TA
–40°C to 125°C
SOIC – D
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Reel of 2500
CD4010BQDRQ1
TOP-SIDE MARKING
CD4021BQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated





 CD4021BQ
CD4021B-Q1
SCHS378 – MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Functional Diagram
Logic Diagram
2
Submit Documentation Feedback
Product Folder Link(s): CD4021B-Q1
Copyright © 2010, Texas Instruments Incorporated





 CD4021BQ
CD4021B-Q1
www.ti.com
SCHS378 – MARCH 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VDD
PD
PD
TA
Tstg
ESD
DC supply voltage range (voltage referenced to VSS terminal)
Input voltage range, all inputs
DC input current, any one input
Power dissipation per package
TA = –40°C to +100°C
TA = +100°C to +125°C
Device dissipation per output transistor
Operating temperature range
Storage temperature range
Electrostatic discharge rating(2)
Human-body model (HBM)
Machine model (MM)
Charged-Device Model (CDM)
Latch-up performance per JESD 78, Class I
VALUE
–0.5 to +20
–0.5 to VDD +0.5
±10
500
Derate Linearity at
12mW/°C to 20 mW
100
–40 to +125
–65 to +150
2000
200
1000
50
UNIT
V
V
mA
mW
mW
°C
°C
V
mA
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested in accordance with AEC-Q100.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CD4021B-Q1
Submit Documentation Feedback
3



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