CMOS Quad 2-Input NAND Gate
Data sheet acquired from Harris Semiconductor SCHS022D – Revised September 2003
The CD4011UB types are supplied in 14-le...
Description
Data sheet acquired from Harris Semiconductor SCHS022D – Revised September 2003
The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright © 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
CD4011UBE CD4011UBEE4
CD4011UBF
CD4011UBM CD4011UBM96 CD4011UBMT CD4011UBNSR CD4011UBPWR
ACTIVE ACTIVE ACTIVE
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
PDIP PDIP CDIP
SOIC SOIC SOIC SO TSSOP
N
14
25 RoHS & Green
N
14
25 RoHS & Green
J
14
1
Non-RoHS
& Green
D
14
50 RoHS & Green
D
14 2500 RoHS & Green
D
14 250 RoHS & Green
NS 14 2000 RoHS & Green
PW 14 2000 RoHS & Green
Lead finish/ Ball material
(6)
NIPDAU NIPDAU
SNPB
NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
MSL Peak Temp Op Temp (°C)
(3)
N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type
-55 to 125 -55 to 125 -55 to 125
Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
Device Marking
(4/5)
CD4011UBE CD4011UBE CD4011UBF
CD4011UBM CD4011UBM CD4011UBM CD4011UB CM011UB
(1) The marketing status values are defined as follows: ACTIVE: Product device...
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