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VOLTAGE SHIFTER. CD40109BQ Datasheet

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VOLTAGE SHIFTER. CD40109BQ Datasheet






CD40109BQ SHIFTER. Datasheet pdf. Equivalent




CD40109BQ SHIFTER. Datasheet pdf. Equivalent





Part

CD40109BQ

Description

CMOS QUAD LOW-TO-HIGH VOLTAGE SHIFTER

Manufacture

Texas Instruments

Datasheet
Download CD40109BQ Datasheet


Texas Instruments CD40109BQ

CD40109BQ; CD40109B-Q1 www.ti.com SCHS380 A – J UNE 2010 – REVISED AUGUST 2011 CMOS Q UAD LOW-TO-HIGH VOLTAGE SHIFTER Check f or Samples: CD40109B-Q1 FEATURES 1 • Qualified for Automotive Applications • Independent of Power Supply Sequenc e Considerations – VCC Can Exceed VDD – Input Signals can Exceed Both VCC and VDD • Up and Down Level-Shifting Capability • Three-State Outputs.


Texas Instruments CD40109BQ

With Separate Enable Controls • Stand ardized Symmetrical Output Characterist ics • 100% Tested for Quiescent Curre nt at 20 V • Maximum Input Current: 1 µA at 18 V Over Full Package-Temp erature Range – 100 nA at 18 V and 25 °C • Noise Margin (Full Package-Temp erature Range): – 1 V at VCC = 5 V, V DD = 10 V – 2 V at VCC = 10 V, VDD = 15 V • 5-V, 10-V, and 15-V Parametri.


Texas Instruments CD40109BQ

c Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, "Stan dard specifications for Description of 'B' Series CMOS Devices" • Latch-Up Performance Meets 50 mA per JESD 78, Cl ass I APPLICATIONS • High-or-Low Leve l-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussin g • Isolation of Logic Subsystem Usin g Separate Power Supplies .



Part

CD40109BQ

Description

CMOS QUAD LOW-TO-HIGH VOLTAGE SHIFTER

Manufacture

Texas Instruments

Datasheet
Download CD40109BQ Datasheet




 CD40109BQ
CD40109B-Q1
www.ti.com
SCHS380 A JUNE 2010 REVISED AUGUST 2011
CMOS QUAD LOW-TO-HIGH VOLTAGE SHIFTER
Check for Samples: CD40109B-Q1
FEATURES
1
Qualified for Automotive Applications
Independent of Power Supply Sequence
Considerations
VCC Can Exceed VDD
Input Signals can Exceed Both VCC and VDD
Up and Down Level-Shifting Capability
Three-State Outputs With Separate Enable
Controls
Standardized Symmetrical Output
Characteristics
100% Tested for Quiescent Current at 20 V
Maximum Input Current:
1 µA at 18 V Over Full
Package-Temperature Range
100 nA at 18 V and 25°C
Noise Margin (Full Package-Temperature
Range):
1 V at VCC = 5 V, VDD = 10 V
2 V at VCC = 10 V, VDD = 15 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13B, "Standard specifications for
Description of 'B' Series CMOS Devices"
Latch-Up Performance Meets 50 mA per JESD
78, Class I
APPLICATIONS
High-or-Low Level-Shifting With Three-State
Outputs for Unidirectional or Bidirectional
Bussing
Isolation of Logic Subsystem Using Separate
Power Supplies from Supply Sequencing,
Supply Loss, and Supply Regulation
Considerations
NS PACKAGE
(TOP VIEW)
DESCRIPTION
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic
input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with
logical 1 = VDD and logical 0 = VSS.
The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the
high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There
are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one
exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the
device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may
exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109
will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled
three-state output controls produces a high-impedance state in the corresponding output.
TA
40°C to 125°C
SOIC NS
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Reel of 2000
CD40109BQNSRQ1
TOP-SIDE MARKING
CD40109BQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 20102011, Texas Instruments Incorporated





 CD40109BQ
CD40109B-Q1
SCHS380 A JUNE 2010 REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TRUTH TABLE(1)
INPUTS
A, B, C, D
0
1
X
ENABLE
A, B, C, D
1
1
0
OUTPUTS
E, F, G, H
0
1
Z
(1) 0 = VSS, 1 = VCC at inputs and VDD at outputs, X = Don't care, Z =
High impedance
Functional Diagram (1 of 4 Units)
Logic Diagram (1 of 4 Units)
2
Copyright © 20102011, Texas Instruments Incorporated





 CD40109BQ
CD40109B-Q1
www.ti.com
SCHS380 A JUNE 2010 REVISED AUGUST 2011
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VDD DC supply voltage range
Output voltage range
Voltages referenced to VSS terminal
All outputs
DC input current
Any one input
TA = 40°C to + 100°C
PD
Power dissipation per package
TA = 100°C to + 125°C
Device dissipation per output transistor
(for TA = full package-temperature range, all package types)
TA
Operating-temperature range
Tstg Storage temperature range
Latch-Up Performance per JESD 78, Class I
VALUE
0.5 to +20
0.5 to VDD + 0.5
±10
500
Derate linearly at
12 mW/°C to 200 mW
100
40 to +125
65 to +150
50
UNIT
V
V
mA
mW
mW
°C
°C
mA
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply-voltage range (for TA = full package-temperature range)
MIN
MAX
UNIT
3
18
V
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
PARAMETER
VO
VIN
VDD
(V)
(V)
(V)
IDD Max Quiescent device current
IOL Min Output low (sink) current
IOH Min Output high (source) current
VOL Max Output voltage: low-level
VOH Min Output voltage: high-level
IIN Max Input current
IOUT Max
VIL Max Input low voltage
VIH Min Input high voltage
0, 5
5
0, 10 10
0, 15 15
0, 20 20
0.4
0, 5
5
0.5 0, 10 10
1.5 0, 15 15
4.6
0, 5
5
2.5
0, 5
5
9.5 0, 10 10
13.5 0, 15 15
0, 5
5
0, 10 10
0, 15 15
0, 5
5
0, 10 10
0, 15 15
0, 18 18
0, 18 18
1, 9
5
10
1.5,
13.5
10
15
1, 9
5
10
1.5,
13.5
10
15
LIMITS AT INDICATED TEMPERATURES (°C)
40 +85 +125
+25
MIN TYP
UNIT
MAX
1
30
30
0.02
1
2
60
60
4
120 120
0.02
2
µA
0.02
4
20
600 600
0.04
20
0.61 0.42 0.36
0.51
1
1.5
1.1
0.9
1.3
2.6
4
2.8
2.4
3.4
6.8
0.61 0.42 0.36 0.51
1
mA
1.8 1.3 1.15
1.6 3.2
1.5 1.1 0.9
1.3 2.6
4
2.8 2.4
3.4 6.8
0.05
0 0.05
0.05
0 0.05
0.05
0 0.05
V
4.95
4.95
5
9.95
9.95
10
14.95
±0.1
±1
±1
±0.4 ±12 ±12
14.95
15
±105
±104
±0.1 µA
±0.4 µA
1.5
1.5
3
3
V
3.5
3.5
7
7
Copyright © 20102011, Texas Instruments Incorporated
3



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