CMOS QUAD D-TYPE FLIP-FLOP
Data sheet acquired from Harris Semiconductor SCHS105C − Revised October 2003
The CD40175B types are supplied in 16-lead...
Description
Data sheet acquired from Harris Semiconductor SCHS105C − Revised October 2003
The CD40175B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
CD40175BE CD40175BEE4 CD40175BF3A
CD40175BM CD40175BM96 CD40175BMT CD40175BNSR CD40175BPWR
ACTIVE ACTIVE ACTIVE
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
PDIP PDIP CDIP
SOIC SOIC SOIC SO TSSOP
N
16
25 RoHS & Green
N
16
25 RoHS & Green
J
16
1
Non-RoHS
& Green
D
16
40 RoHS & Green
D
16 2500 RoHS & Green
D
16 250 RoHS & Green
NS 16 2000 RoHS & Green
PW 16 2000 RoHS & Green
Lead finish/ Ball material
(6)
NIPDAU NIPDAU
SNPB
NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
MSL Peak Temp Op Temp (°C)
(3)
N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type
-55 to 125 -55 to 125 -55 to 125
Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
Device Marking
(4/5)
CD40175BE CD40175BE CD40175BF3A
CD40175BM CD40175BM CD40175BM CD40175B CM0175B
(1) The marketing status values are defined as follows: ACTIVE: Product devi...
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