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ANALOG-TO-DIGITAL CONVERTER. TLC0838C Datasheet

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ANALOG-TO-DIGITAL CONVERTER. TLC0838C Datasheet






TLC0838C CONVERTER. Datasheet pdf. Equivalent




TLC0838C CONVERTER. Datasheet pdf. Equivalent





Part

TLC0838C

Description

8-BIT ANALOG-TO-DIGITAL CONVERTER



Feature


TLC0834C, TLC0834I, TLC0838C, TLC0838I 8 -BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL D 8-Bit Resolution D Ea sy Microprocessor Interface or Stand-Al one Operation D Operates Ratiometricall y or With 5-V Reference D 4- or 8-Chann el Multiplexer Options With Address Log ic D Input Range 0 to 5 V With Single 5 -V Supply D Remote Operation With Seria l Data Link SLAS0.
Manufacture

Texas Instruments

Datasheet
Download TLC0838C Datasheet


Texas Instruments TLC0838C

TLC0838C; 94E – MARCH 1995 – REVISED OCTOBER 2 000 D Inputs and Outputs Are Compatible With TTL and MOS D Conversion Time of 32 µs at fclock = 250 kHz D Functional ly Equivalent to the ADC0834 and ADC083 8 Without the Internal Zener Regulator Network D Total Unadjusted Error . . . ±1 LSB description These devices are 8-bit successive- approximation analog -to-digital converters, .


Texas Instruments TLC0838C

each with an input-configurable multicha nnel multiplexer and serial input/outpu t. The serial input/ output is configur ed to interface with standard shift reg isters or microprocessors. Detailed inf ormation on interfacing with most popul ar microprocessors is readily available from the factory. The TLC0834 (4-chan nel) and TLC0838 (8-channel) multiplexe r is software-conf.


Texas Instruments TLC0838C

igured for single-ended or differential inputs as well as pseudodifferential in put assignments. The differential analo g voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the v oltage reference input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of res olution. The TLC0.

Part

TLC0838C

Description

8-BIT ANALOG-TO-DIGITAL CONVERTER



Feature


TLC0834C, TLC0834I, TLC0838C, TLC0838I 8 -BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL D 8-Bit Resolution D Ea sy Microprocessor Interface or Stand-Al one Operation D Operates Ratiometricall y or With 5-V Reference D 4- or 8-Chann el Multiplexer Options With Address Log ic D Input Range 0 to 5 V With Single 5 -V Supply D Remote Operation With Seria l Data Link SLAS0.
Manufacture

Texas Instruments

Datasheet
Download TLC0838C Datasheet




 TLC0838C
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
D 8-Bit Resolution
D Easy Microprocessor Interface or
Stand-Alone Operation
D Operates Ratiometrically or With 5-V
Reference
D 4- or 8-Channel Multiplexer Options With
Address Logic
D Input Range 0 to 5 V With Single 5-V Supply
D Remote Operation With Serial Data Link
SLAS094E – MARCH 1995 – REVISED OCTOBER 2000
D Inputs and Outputs Are Compatible With
TTL and MOS
D Conversion Time of 32 µs at
fclock = 250 kHz
D Functionally Equivalent to the ADC0834
and ADC0838 Without the Internal Zener
Regulator Network
D Total Unadjusted Error . . . ±1 LSB
description
These devices are 8-bit successive- approximation analog-to-digital converters, each with an
input-configurable multichannel multiplexer and serial input/output. The serial input/ output is configured to
interface with standard shift registers or microprocessors. Detailed information on interfacing with most popular
microprocessors is readily available from the factory.
The TLC0834 (4-channel) and TLC0838 (8-channel) multiplexer is software-configured for single-ended or
differential inputs as well as pseudodifferential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TLC0834C and TLC0838C are characterized for operation from 0°C to 70°C. The TLC0834I and TLC0838I
are characterized for operation from – 40°C to 85°C. The TLC0834Q is characterized for operation from – 40°C
to 125°C.
TLC0834 . . . D OR N PACKAGE
(TOP VIEW)
TLC0834 . . . PW PACKAGE
(TOP VIEW)
TLC0838 . . . PW, DW, OR N PACKAGE
(TOP VIEW)
NC 1
CS 2
CH0 3
CH1 4
CH2 5
CH3 6
DGTL GND 7
14 VCC
13 DI
12 CLK
11 SARS
10 DO
9 REF
8 ANLG GND
NC 1
16 VCC
CH0 1
CS 2 15 NC
CH1 2
CH0 3 14 CS
CH2 3
CH1 4 13 SARS
CH3 4
CH2 5 12 DO
CH4 5
CH3 6
11 REF
CH5 6
DGTL GND 7 10 ANLG GND
CH6 7
NC 8
9 NC
CH7 8
NC – No internal connection
COM 9
DGTL GND 10
20 VCC
19 NC
18 CS
17 DI
16 CLK
15 SARS
14 DO
13 SE
12 REF
11 ANLG GND
TA
0°C to 70°C
– 40°C to 85°C
– 40°C to 125°C
SMALL
OUTLINE
(D)
TLC0834CD
TLC0834ID
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(DW)
PLASTIC DIP
(N)
TLC0838CDW TLC0834CN TLC0838CN
TLC0838IDW TLC0834IN TLC0838IN
TLC0834QN
TSSOP
(PW)
TLC0834CPW TLC0838CPW
TLC0834IPW TLC0838IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
1




 TLC0838C
functional block diagram
CLK 16
18
CS
DI17
(see Note A)
D
R
5-Bit Shift Register
CLK
SELECT0 SELECT1 ODD\ EVEN SGL\ DIF START
TLC0838
Only
SE
TLC0834
TLC0838
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
To Internal
Circuits
Analog
MUX
EN
Start
Flip-Flop
CLK
S
R
CS
18
15
SARS
Time
Delay
CLK
S
R
18
CS
12
REF
EN
Ladder
and
Decoder
Comparator
CS
18
R
Bits 0–7
SAR
Logic
and
Latch
Bits 0–7
Bit 1
CS
18
R
CLK
9-Bit
Shift
Register
EOC
One
Shot
MSB
First
LSB
First
CS
18
R
CLK
D
CS
18
14
DO
NOTES A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
B: Terminal numbers shown are for the DW or N package.




 TLC0838C
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094E – MARCH 1995 – REVISED OCTOBER 2000
functional description
The TLC0834 and TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudodifferential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLC0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed
by address information.
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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