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Analog-to-Digital Converters. TLC1543-EP Datasheet

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Analog-to-Digital Converters. TLC1543-EP Datasheet






TLC1543-EP Converters. Datasheet pdf. Equivalent




TLC1543-EP Converters. Datasheet pdf. Equivalent





Part

TLC1543-EP

Description

10-Bit Analog-to-Digital Converters



Feature


TLC1542ĆEP, TLC1543ĆEP 10ĆBIT ANALOG TOĆDIGITAL CONVERTERS WITH SERIAL CON TROL AND 11 ANALOG INPUTS SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006 D Controlled Baseline − One Assembly /Test Site, One Fabrication Site D Exte nded Temperature Performance of −40° C to 125°C D Enhanced Diminishing Manu facturing Sources (DMS) Support D Enhan ced Product Change Notification D.
Manufacture

Texas Instruments

Datasheet
Download TLC1543-EP Datasheet


Texas Instruments TLC1543-EP

TLC1543-EP; Qualification Pedigree† D 10-Bit Reso lution A/D Converter D 11 Analog Input Channels D Three Built-In Self-Test Mod es D Inherent Sample-and-Hold Function D Total Unadjusted Error . . . ± 1 LSB Max D On-Chip System Clock D End-of-Co nversion (EOC) Output D Terminal Compat ible With TLC542 D CMOS Technology DW PACKAGE (TOP VIEW) A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 .


Texas Instruments TLC1543-EP

A8 9 GND 10 20 VCC 19 EOC 18 I/O CLOCK 17 ADDRESS 16 DATA OUT 15 CS 14 REF + 1 3 REF − 12 A10 11 A9 description The TLC1542-EP and TLC1543-EP are CMOS 10- bit switched-capacitor successive-appro ximation analog-to-digital converters. These devices have three inputs, a 3-st ate output chip select (CS), input/outp ut clock (I/O CLOCK), address input (AD DRESS), and data out.


Texas Instruments TLC1543-EP

put (DATA OUT)] that provide a direct 4- wire interface to the serial port of a host processor. The TLC1542-EP and TLC1 543-EP allow high-speed data transfers from the host. In addition to a high-sp eed A /D converter and versatile contro l capability, the TLC1542-EP and TLC154 3-EP have an on-chip 14-channel multipl exer that can select any one of 11 anal og inputs or any o.

Part

TLC1543-EP

Description

10-Bit Analog-to-Digital Converters



Feature


TLC1542ĆEP, TLC1543ĆEP 10ĆBIT ANALOG TOĆDIGITAL CONVERTERS WITH SERIAL CON TROL AND 11 ANALOG INPUTS SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006 D Controlled Baseline − One Assembly /Test Site, One Fabrication Site D Exte nded Temperature Performance of −40° C to 125°C D Enhanced Diminishing Manu facturing Sources (DMS) Support D Enhan ced Product Change Notification D.
Manufacture

Texas Instruments

Datasheet
Download TLC1543-EP Datasheet




 TLC1543-EP
TLC1542ĆEP, TLC1543ĆEP
10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree
D 10-Bit Resolution A/D Converter
D 11 Analog Input Channels
D Three Built-In Self-Test Modes
D Inherent Sample-and-Hold Function
D Total Unadjusted Error . . . ± 1 LSB Max
D On-Chip System Clock
D End-of-Conversion (EOC) Output
D Terminal Compatible With TLC542
D CMOS Technology
DW PACKAGE
(TOP VIEW)
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 EOC
18 I/O CLOCK
17 ADDRESS
16 DATA OUT
15 CS
14 REF +
13 REF −
12 A10
11 A9
description
The TLC1542-EP and TLC1543-EP are CMOS 10-bit switched-capacitor successive-approximation
analog-to-digital converters. These devices have three inputs, a 3-state output chip select (CS), input/output
clock (I/O CLOCK), address input (ADDRESS), and data output (DATA OUT)] that provide a direct 4-wire
interface to the serial port of a host processor. The TLC1542-EP and TLC1543-EP allow high-speed data
transfers from the host.
In addition to a high-speed A /D converter and versatile control capability, the TLC1542-EP and TLC1543-EP
have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal
self-test voltages. The sample-and-hold function is automatic. At the end of the A /D conversion, the
end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated
in the TLC1542-EP and TLC1543-EP features differential high-impedance reference inputs that facilitate
ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A
switched-capacitor design allows low-error conversion over the full operating free-air temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright 2006, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TLC1543-EP
TLC1542ĆEP, TLC1543ĆEP
10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(DW)
−40°C to 125°C
TLC1542QDWREP{
TLC1543QDWREP
This part number is in the product preview stage
of development.
functional block diagram
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A9 11
A10 12
14-Channel
Analog
Multiplexer
Sample and
Hold
4 Input Address
Register
REF+
14
REF −
13
10-Bit
Analog-to-Digital
Converter
(Switched Capacitors)
10
Output
10
Data
Register
3
17
ADDRESS
18
I/O CLOCK
15
CS
Self-Test
Reference
System
Clock,
Control Logic,
and I/O
Counters
10-to-1 Data
Selector and
Driver
16 DATA
OUT
4
19
EOC
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
1 kTYP
A0 −A10
Ci = 60 pF TYP
(equivalent input
capacitance)
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
A0 −A10
5 MTYP
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC1543-EP
TLC1542ĆEP, TLC1543ĆEP
10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006
Terminal Functions
TERMINAL
NAME
NO.
ADDRESS
17
A0 −A10
CS
1 −9,
11, 12
15
DATA OUT
16
EOC
19
GND
10
I/O CLOCK
18
REF +
14
REF −
13
VCC
20
I/O
DESCRIPTION
I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be
converted next. The address data is presented with the MSB first and shifts in on the first four rising edges
of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for
the remainder of the current conversion period.
I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The
driving source impedance should be less than or equal to 1 k.
I Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA
OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal
system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling
edges of the internal system clock.
O The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant
bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK.
On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data
transfers of more than ten clocks produce zeroes as the unused LSBs.
O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data is ready for transfer.
I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to this terminal.
I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK
with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
I The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage
range is determined by the difference between the voltage applied to this terminal and the voltage applied
to the REF − terminal.
I The lower reference voltage value (nominally ground) is applied to this terminal.
I Positive supply voltage
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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