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Buck Converter. TPS54292 Datasheet

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Buck Converter. TPS54292 Datasheet






TPS54292 Converter. Datasheet pdf. Equivalent




TPS54292 Converter. Datasheet pdf. Equivalent





Part

TPS54292

Description

Fully-Synchronous Buck Converter



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 TPS5429x 1.5-A and 2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET 1 Features •1 4.5-V to 18-V Input Range • Output V oltage Range 0.8 V to DMAX × VIN • F ully Integrated Dual Buck: 1..
Manufacture

Texas Instruments

Datasheet
Download TPS54292 Datasheet


Texas Instruments TPS54292

TPS54292; 5 A and 2.5 A • Three Fixed Switching Frequency Versions: – TPS54290: 300 k Hz – TPS54291: 600 kHz – TPS54292: 1.2 MHz • Integrated UVLO • 0.8 VRE F With 1% Accuracy (0°C to 85°C) • Internal Soft Start: – TPS54290: 5.2 ms – TPS54291: 2.6 ms – TPS54292: 1 .3 ms • Dual PWM Outputs 180° Out-of -Phase • Dedicated Enable for Each Ch annel • Current Mode Control for Simplified C.


Texas Instruments TPS54292

ompensation • External Compensation Pulse-by-Pulse Overcurrent Protection , 2.2-A and 3.8-A Overcurrent Limit • Integrated Bootstrap Switch • Therma l Shutdown Protection at 145°C • 16- Pin PowerPAD™ HTSSOP Package 3 Descr iption The TPS54290, TPS54291, and TPS5 4292 devices are dual-output, fully syn chronous buck converters capable of sup porting applications with a min.


Texas Instruments TPS54292

imal number of external components. It o perates from a 4.5-V to 18-V input supp ly voltage, and supports output voltage s as low as 0.8 V and as high as 90% of the input voltage. Both high-side and low-side MOSFETs are integrated to prov ide fully synchronous conversion with h igher efficiency. Channel 1 can provide up to 1.5 A of continuous current. Mea nwhile, Channel 2 .

Part

TPS54292

Description

Fully-Synchronous Buck Converter



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 TPS5429x 1.5-A and 2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET 1 Features •1 4.5-V to 18-V Input Range • Output V oltage Range 0.8 V to DMAX × VIN • F ully Integrated Dual Buck: 1..
Manufacture

Texas Instruments

Datasheet
Download TPS54292 Datasheet




 TPS54292
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TPS54290, TPS54291, TPS54292
SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016
TPS5429x 1.5-A and 2.5-A Dual, Fully-Synchronous
Buck Converter With Integrated MOSFET
1 Features
1 4.5-V to 18-V Input Range
• Output Voltage Range 0.8 V to DMAX × VIN
• Fully Integrated Dual Buck: 1.5 A and 2.5 A
• Three Fixed Switching Frequency Versions:
– TPS54290: 300 kHz
– TPS54291: 600 kHz
– TPS54292: 1.2 MHz
• Integrated UVLO
• 0.8 VREF With 1% Accuracy (0°C to 85°C)
• Internal Soft Start:
– TPS54290: 5.2 ms
– TPS54291: 2.6 ms
– TPS54292: 1.3 ms
• Dual PWM Outputs 180° Out-of-Phase
• Dedicated Enable for Each Channel
• Current Mode Control for Simplified
Compensation
• External Compensation
• Pulse-by-Pulse Overcurrent Protection,
2.2-A and 3.8-A Overcurrent Limit
• Integrated Bootstrap Switch
• Thermal Shutdown Protection at 145°C
• 16-Pin PowerPAD™ HTSSOP Package
3 Description
The TPS54290, TPS54291, and TPS54292 devices
are dual-output, fully synchronous buck converters
capable of supporting applications with a minimal
number of external components. It operates from a
4.5-V to 18-V input supply voltage, and supports
output voltages as low as 0.8 V and as high as 90%
of the input voltage.
Both high-side and low-side MOSFETs are integrated
to provide fully synchronous conversion with higher
efficiency. Channel 1 can provide up to 1.5 A of
continuous current. Meanwhile, Channel 2 supports
up to 2.5 A.
Current mode control simplifies the compensation.
The external compensation adds flexibility for the
user to choose different type of output capacitors.
180° out-of-phase operation reduces the ripple
current through the input capacitor, providing the
benefit of reducing input capacitance, alleviating EMI
and increasing capacitor life.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54290
TPS54291
TPS54292
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Set-Top Boxes
• Digital TVs
• Power for DSP
• Consumer Electronics
Simplified Schematic
VIN
VOUT1
TPS54290
1 PVDD1 PVDD2 16
2 BOOT1 BOOT2 15
3 SW1
SW2 14
4 PGND1 PGND2 13
5 EN1
BP 12
6 EN2
GND 11
7 FB1
FB2 10
8 COMP1 COMP2 9
GND
VOUT2
UDG-09130
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 TPS54292
TPS54290, TPS54291, TPS54292
SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics .............................................. 8
8 Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 17
9 Application and Implementation ........................ 18
9.1 Application Information .......................................... 18
9.2 Typical Applications ................................................ 18
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Examples................................................... 26
11.3 Overtemperature Protection and Junction
Temperature Rise .................................................... 27
11.4 Power Derating ..................................................... 28
12 Device and Documentation Support ................. 29
12.1 Documentation Support ........................................ 29
12.2 Related Links ........................................................ 29
12.3 Receiving Notification of Documentation Updates 29
12.4 Community Resources.......................................... 29
12.5 Trademarks ........................................................... 29
12.6 Electrostatic Discharge Caution ............................ 29
12.7 Glossary ................................................................ 29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2009) to Revision A
Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
• Deleted Lead temperature (260°C maximum)........................................................................................................................ 5
• Added Thermal Information table to replace the Package Dissipation Ratings table ............................................................ 5
2
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TPS54290 TPS54291 TPS54292




 TPS54292
www.ti.com
5 Device Comparison Table
TPS54290, TPS54291, TPS54292
SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016
DEVICE
TPS40222
TPS5428x
TPS5538x
DESCRIPTION
5-V Input, 1.5-A, Non-Synchronous Buck Converter
2-A Dual Non-Synchronous Converter with Integrated High-Side FET
3-A Dual Non-Synchronous Converter with Integrated High-Side FET
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
PVDD1
1
BOOT1
2
SW1
3
PGND1
4
EN1
5
EN2
6
FB1
7
COMP1
8
16
PVDD2
15
BOOT2
14
SW2
13
PGND2
Thermal Pad
12
BP
11
GND
10
FB2
9
COMP2
Not to scale
Pin Functions
PIN
I/O
NO.
NAME
DESCRIPTION
Power input to the Output1 high-side MOSFET only. This pin must be locally bypassed to
1
PVDD1
I
PGND1 with a low-ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be
tied externally together.
Input supply to the high-side gate driver for Output1. Connect a 22-nF to 68-nF capacitor from
this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch.
2
BOOT1
I
The switch is turned ON during the off-time of the converter. To slow down the turn ON of the
internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap
capacitor.
3
SW1
O Source (switching) output for Output1 PWM
4
PGND1
Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to
the internal logic circuits.
Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is
5
EN1
I
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow
soft start of Output1 to begin. An internal current source drives this pin to PVDD2 if left
floating. Connect this pin to GND to bypass the enable function.
Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is
6
EN2
I
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow
soft start of Output2 to begin. An internal current source drives this pin to PVDD2 if left
floating. Connect this pin to GND to bypass the enable function.
Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the
7
FB1
I
PWM for Outputx to regulate the voltage at this pin to the internal 0.8-V reference. A series
resistor divider from Outputx to ground, with the center connection tied to this pin, determines
the value of the regulated output voltage.
8
COMP1
O
Output of the transconductance (gM) amplifier. A R-C compensation network is connected
from COMPx to GND.
Copyright © 2009–2016, Texas Instruments Incorporated
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