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BUS SWITCH. SN74CBT3306 Datasheet

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BUS SWITCH. SN74CBT3306 Datasheet






SN74CBT3306 SWITCH. Datasheet pdf. Equivalent




SN74CBT3306 SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3306

Description

DUAL FET BUS SWITCH



Feature


SN74CBT3306 DUAL FET BUS SWITCH D 5-Ω Switch Connection Between Two Ports D T TL-Compatible Input Levels description/ ordering information The SN74CBT3306 du al FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. SCDS016H − MAY 1995 REVISED JANUARY 2004 D OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3306 Datasheet


Texas Instruments SN74CBT3306

SN74CBT3306; 1B 3 GND 4 8 VCC 7 2OE 6 2B 5 2A ORDE RING INFORMATION TA PACKAGE† ORDER ABLE PART NUMBER TOP-SIDE MARKING − 40°C to 85°C SOIC − D TSSOP − PW Tube Tape and reel Tube Tape and reel SN74CBT3306D SN74CBT3306DR SN74CBT330 6PW SN74CBT3306PWR CU306 CU306 † Pa ckage drawings, standard packing quanti ties, thermal data, symbolization, and PCB design guidelines are avai.


Texas Instruments SN74CBT3306

lable at www.ti.com/sc/package. FUNCTIO N TABLE (each bus switch) INPUT OE F UNCTION L A port = B port H Disconne ct logic diagram (positive logic) 2 1 A 1 1OE 5 2A 7 2OE 3 1B 6 2B Pleas e be aware that an important notice con cerning availability, standard warranty , and use in critical applications of T exas Instruments semiconductor products and disclaimers t.


Texas Instruments SN74CBT3306

hereto appears at the end of this data s heet. PRODUCTION DATA information is c urrent as of publication date. Products conform to specifications per the term s of Texas Instruments standard warrant y. Production processing does not neces sarily include testing of all parameter s. • POST OFFICE BOX 655303 DALLAS, T EXAS 75265 Copyright © 2004, Texas In struments Incorporate.

Part

SN74CBT3306

Description

DUAL FET BUS SWITCH



Feature


SN74CBT3306 DUAL FET BUS SWITCH D 5-Ω Switch Connection Between Two Ports D T TL-Compatible Input Levels description/ ordering information The SN74CBT3306 du al FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. SCDS016H − MAY 1995 REVISED JANUARY 2004 D OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3306 Datasheet




 SN74CBT3306
SN74CBT3306
DUAL FET BUS SWITCH
D 5-Ω Switch Connection Between Two Ports
D TTL-Compatible Input Levels
description/ordering information
The SN74CBT3306 dual FET bus switch features
independent line switches. Each switch is
disabled when the associated output-enable (OE)
input is high.
SCDS016H − MAY 1995 − REVISED JANUARY 2004
D OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
GND 4
8 VCC
7 2OE
6 2B
5 2A
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tube
Tape and reel
Tube
Tape and reel
SN74CBT3306D
SN74CBT3306DR
SN74CBT3306PW
SN74CBT3306PWR
CU306
CU306
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L A port = B port
H
Disconnect
logic diagram (positive logic)
2
1A
1
1OE
5
2A
7
2OE
3
1B
6
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2004, Texas Instruments Incorporated
1




 SN74CBT3306
SN74CBT3306
DUAL FET BUS SWITCH
SCDS016H − MAY 1995 − REVISED JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH
High-level control input voltage
2
V
VIL
Low-level control input voltage
0.8 V
TA
Operating free-air temperature
−40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPMAX UNIT
VIK
VCC = 4.5 V,
II = −18 mA
−1.2 V
II
VCC = 5.5 V,
VI = 5.5 V or GND
±1 μA
ICC
ΔICC§
VCC = 5.5 V,
Control inputs VCC = 5.5 V,
IO = 0,
VI = VCC or GND
One input at 3.4 V, Other inputs at VCC or GND
3 μA
2.5 mA
Ci
Control inputs VI = 3 V or 0
3
pF
Cio(OFF)
VO = 3 V or 0,
OE = VCC
4
pF
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
II = 15 mA
14
20
ron¶
VCC = 4.5 V
VI = 0
II = 64 mA
II = 30 mA
5
7Ω
5
7
VI = 2.4 V,
II = 15 mA
10
15
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74CBT3306
SN74CBT3306
DUAL FET BUS SWITCH
SCDS016H − MAY 1995 − REVISED JANUARY 2004
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd†
FROM
(INPUT)
A or B
TO
(OUTPUT)
B or A
VCC = 4 V
MIN MAX
0.35
VCC = 5 V
± 0.5 V
MIN MAX
0.25
UNIT
ns
ten
OE
A or B
5.6 1.8
5 ns
tdis
OE
A or B
4.6
1 4.3 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
From Output
Under Test
CL = 50 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
7V
S1
Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT
Output
Control
1.5 V
3V
1.5 V
0V
Input
tPLH
Output
1.5 V
3V
1.5 V
0V
tPHL
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
1.5 V
VOL
tPZL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZH
1.5 V
1.5 V
tPLZ
3.5 V
VOL + 0.3 V
VOL
tPHZ
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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