DatasheetsPDF.com

BUS SWITCH. SN74CBT3306C Datasheet

DatasheetsPDF.com

BUS SWITCH. SN74CBT3306C Datasheet






SN74CBT3306C SWITCH. Datasheet pdf. Equivalent




SN74CBT3306C SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3306C

Description

DUAL FET BUS SWITCH



Feature


SN74CBT3306C DUAL FET BUS SWITCH 5ĆV BU S SWITCH WITH ć2ĆV UNDERSHOOT PROTECT ION SCDS127A − SEPTEMBER 2003 − REV ISED OCTOBER 2003 D Undershoot Protect ion for Off-Isolation on A and B Ports Up To −2 V D Bidirectional Data Flow, With Near-Zero Propagation Delay D Low ON-State Resistance (ron) Characterist ics (ron = 3 Ω Typical) D Low Input/O utput Capacitance Minimizes L.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3306C Datasheet


Texas Instruments SN74CBT3306C

SN74CBT3306C; oading and Signal Distortion (Cio(OFF) = 5 pF Typical) D Data and Control Input s Provide Undershoot Clamp Diodes D Low Power Consumption (ICC = 3 µA Max) D VCC Operating Range From 4 V to 5.5 V D Data I/Os Support 0 to 5-V Signaling L evels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5- V, 3.3-V, 5-V) D Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Output s D Ioff Supports P.


Texas Instruments SN74CBT3306C

artial-Power-Down Mode Operation D Latch -Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged- Device Model (C101) D Supports Both Dig ital and Analog Applications: USB Inter face, Bus Isolation, Low-Distortion Sig nal Gating D OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1B 3 GND 4.


Texas Instruments SN74CBT3306C

8 VCC 7 2OE 6 2B 5 2A description/ord ering information The SN74CBT3306C is a high-speed TTL-compatible FET bus swit ch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT330 6C provides protection for undershoot u p to −2 V by sensing an undershoot ev ent and ensuring tha.

Part

SN74CBT3306C

Description

DUAL FET BUS SWITCH



Feature


SN74CBT3306C DUAL FET BUS SWITCH 5ĆV BU S SWITCH WITH ć2ĆV UNDERSHOOT PROTECT ION SCDS127A − SEPTEMBER 2003 − REV ISED OCTOBER 2003 D Undershoot Protect ion for Off-Isolation on A and B Ports Up To −2 V D Bidirectional Data Flow, With Near-Zero Propagation Delay D Low ON-State Resistance (ron) Characterist ics (ron = 3 Ω Typical) D Low Input/O utput Capacitance Minimizes L.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3306C Datasheet




 SN74CBT3306C
SN74CBT3306C
DUAL FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (ron)
Characteristics (ron = 3 Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(ICC = 3 µA Max)
D VCC Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
D OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
GND 4
8 VCC
7 2OE
6 2B
5 2A
description/ordering information
The SN74CBT3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3306C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B
ports.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tube
Tape and reel
Tube
Tape and reel
SN74CBT3306CD
SN74CBT3306CDR
SN74CBT3306CPW
SN74CBT3306CPWR
CU306C
CU306C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




 SN74CBT3306C
SN74CBT3306C
DUAL FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
INPUT
OE
L
H
FUNCTION TABLE
(each bus switch)
INPUT/OUTPUT
A
FUNCTION
B
A port = B port
Z
Disconnect
logic diagram (positive logic)
2
1A
1
1OE
3
SW
1B
5
2A
7
2OE
6
SW
2B
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN
EN is the internal enable signal applied to the switch.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74CBT3306C
SN74CBT3306C
DUAL FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH High-level control input voltage
2 5.5 V
VIL Low-level control input voltage
0 0.8 V
VI/O Data input/output voltage
0 5.5 V
TA Operating free-air temperature
−40 85 °C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






Recommended third-party SN74CBT3306C Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)