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BUS SWITCH. SN74CBT3345 Datasheet

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BUS SWITCH. SN74CBT3345 Datasheet






SN74CBT3345 SWITCH. Datasheet pdf. Equivalent




SN74CBT3345 SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3345

Description

8-BIT FET BUS SWITCH



Feature


SN74CBT3345 8ĆBIT FET BUS SWITCH D Sta ndard ’245-Type Pinout D 5-Ω Switch Connection Between Two Ports D TTL-Com patible Input Levels description/orderi ng information The SN74CBT3345 provides eight bits of high-speed TTL-compatibl e bus switching in a standard ’245 de vice pinout. The low on-state resistanc e of the switch allows connections to b e made with minimal propa.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3345 Datasheet


Texas Instruments SN74CBT3345

SN74CBT3345; gation delay. The device is organized as one 8-bit switch bank with dual output -enable (OE and OE) inputs. When OE is low or OE is high, the switch is on, an d port A is connected to port B. When O E is high and OE is low, the switch is open, and the high-impedance state exis ts between the two ports. SCDS027I − MAY 1995 − REVISED JANUARY 2004 DB, DBQ, DGV, DW, OR PW PA.


Texas Instruments SN74CBT3345

CKAGE (TOP VIEW) OE 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10 20 VCC 1 9 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B 6 12 B7 11 B8 ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TO P-SIDE MARKING SOIC − DW Tube Tape and reel SN74CBT3345DW SN74CBT3345DWR CBT3345 SSOP − DB Tape and reel SN 74CBT3345DBR CU345 −40°C to 85°C S SOP (QSOP) − DBQ Tape and re.


Texas Instruments SN74CBT3345

el SN74CBT3345DBQR CBT3345 TSSOP − PW Tube Tape and reel SN74CBT3345PW SN7 4CBT3345PWR CU345 TVSOP − DGV Tape and reel SN74CBT3345DGVR CU345 † Pa ckage drawings, standard packing quanti ties, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE OE FUNCTION H X A port = B port X L A port .

Part

SN74CBT3345

Description

8-BIT FET BUS SWITCH



Feature


SN74CBT3345 8ĆBIT FET BUS SWITCH D Sta ndard ’245-Type Pinout D 5-Ω Switch Connection Between Two Ports D TTL-Com patible Input Levels description/orderi ng information The SN74CBT3345 provides eight bits of high-speed TTL-compatibl e bus switching in a standard ’245 de vice pinout. The low on-state resistanc e of the switch allows connections to b e made with minimal propa.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3345 Datasheet




 SN74CBT3345
SN74CBT3345
8ĆBIT FET BUS SWITCH
D Standard ’245-Type Pinout
D 5-Switch Connection Between Two Ports
D TTL-Compatible Input Levels
description/ordering information
The SN74CBT3345 provides eight bits of
high-speed TTL-compatible bus switching in a
standard ’245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as one 8-bit switch bank
with dual output-enable (OE and OE) inputs.
When OE is low or OE is high, the switch is on, and
port A is connected to port B. When OE is high and
OE is low, the switch is open, and the
high-impedance state exists between the two
ports.
SCDS027I − MAY 1995 − REVISED JANUARY 2004
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74CBT3345DW
SN74CBT3345DWR
CBT3345
SSOP − DB
Tape and reel SN74CBT3345DBR CU345
−40°C to 85°C SSOP (QSOP) − DBQ Tape and reel SN74CBT3345DBQR CBT3345
TSSOP − PW
Tube
Tape and reel
SN74CBT3345PW
SN74CBT3345PWR
CU345
TVSOP − DGV
Tape and reel SN74CBT3345DGVR CU345
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
OE
FUNCTION
H
X
A port = B port
X
L
A port = B port
L
H
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
1




 SN74CBT3345
SN74CBT3345
8ĆBIT FET BUS SWITCH
SCDS027I − MAY 1995 − REVISED JANUARY 2004
logic diagram (positive logic)
2
A1
18
B1
9
A8
1
OE
19
OE
11
B8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage
4.5 5.5 V
VIH High-level control input voltage
2
V
VIL Low-level control input voltage
0.8 V
TA Operating free-air temperature
−40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74CBT3345
SN74CBT3345
8ĆBIT FET BUS SWITCH
SCDS027I − MAY 1995 − REVISED JANUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
VIK
VCC = 4.5 V,
II = −18 mA
−1.2 V
II
All inputs
VCC = 5.5 V,
VI = 5.5 V or GND
±1 µA
ICC
ICC‡
VCC = 5.5 V,
Control inputs VCC = 5.5 V,
IO = 0,
One input at 3.4 V,
VI = VCC or GND
Other inputs at VCC or GND
50 µA
3.5 mA
Ci
Control inputs VI = 3 V or 0
3
pF
Cio(OFF)
VO = 3 V or 0,
OE = VCC or OE = GND
6
pF
ron§
VCC = 4.5 V
VI = 0
II = 64 mA
II = 30 mA
5
7
5
7
VI = 2.4 V,
II = 15 mA
10
15
All typical values are at VCC = 5 V, TA = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd¶
FROM
(INPUT)
A or B
TO
(OUTPUT)
B or A
VCC = 5 V
± 0.5 V
MIN MAX
0.25
UNIT
ns
ten
OE or OE
A or B
1 9.1 ns
tdis
OE or OE
A or B
1 8.7 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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