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BUS SWITCH. SN74CBT3125C Datasheet

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BUS SWITCH. SN74CBT3125C Datasheet






SN74CBT3125C SWITCH. Datasheet pdf. Equivalent




SN74CBT3125C SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3125C

Description

QUADRUPLE FET BUS SWITCH



Feature


SN74CBT3125C QUADRUPLE FET BUS SWITCH 5 V BUS SWITCH WITH ć2ĆV UNDERSHOOT PR OTECTION SCDS122A − JULY 2003 − REV ISED OCTOBER 2003 D Undershoot Protect ion for Off-Isolation on A and B Ports Up To −2 V D Bidirectional Data Flow, With Near-Zero Propagation Delay D Low ON-State Resistance (ron) Characterist ics (ron = 3 Ω Typical) D Low Input/O utput Capacitance Minimizes L.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3125C Datasheet


Texas Instruments SN74CBT3125C

SN74CBT3125C; oading and Signal Distortion (Cio(OFF) = 5 pF Typical) D Data and Control Input s Provide Undershoot Clamp Diodes D Low Power Consumption (ICC = 3 µA Max) D VCC Operating Range From 4 V to 5.5 V D Data I/Os Support 0 to 5-V Signaling L evels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5- V, 3.3-V, 5-V) D Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Output s D Ioff Supports P.


Texas Instruments SN74CBT3125C

artial-Power-Down Mode Operation D Latch -Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged- Device Model (C101) D Supports Both Dig ital and Analog Applications: USB Inter face, Bus Isolation, Low-Distortion Sig nal Gating D, DB, DGV, OR PW PACKAGE ( TOP VIEW) 1OE 1 1A 2 .


Texas Instruments SN74CBT3125C

1B 3 2OE 4 2A 5 2B 6 GND 7 14 VCC 13 4O E 12 4A 11 4B 10 3OE 9 3A 8 3B RGY PAC KAGE (TOP VIEW) 1OE VCC 1 1A 2 1B 3 2 OE 4 2A 5 2B 6 7 14 13 4OE 12 4A 11 4B 10 3OE 9 3A 8 DBQ PACKAGE (TOP VIEW) NC 1 1OE 2 1A 3 1B 4 2OE 5 2A 6 2B 7 G ND 8 16 VCC 15 4OE 14 4A 13 4B 12 3OE 11 3A 10 3B 9 NC NC − No internal co nnection GND 3B description/ordering information The SN74.

Part

SN74CBT3125C

Description

QUADRUPLE FET BUS SWITCH



Feature


SN74CBT3125C QUADRUPLE FET BUS SWITCH 5 V BUS SWITCH WITH ć2ĆV UNDERSHOOT PR OTECTION SCDS122A − JULY 2003 − REV ISED OCTOBER 2003 D Undershoot Protect ion for Off-Isolation on A and B Ports Up To −2 V D Bidirectional Data Flow, With Near-Zero Propagation Delay D Low ON-State Resistance (ron) Characterist ics (ron = 3 Ω Typical) D Low Input/O utput Capacitance Minimizes L.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3125C Datasheet




 SN74CBT3125C
SN74CBT3125C
QUADRUPLE FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS122A − JULY 2003 − REVISED OCTOBER 2003
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (ron)
Characteristics (ron = 3 Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(ICC = 3 µA Max)
D VCC Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
2OE 4
2A 5
2B 6
GND 7
14 VCC
13 4OE
12 4A
11 4B
10 3OE
9 3A
8 3B
RGY PACKAGE
(TOP VIEW)
1
1A 2
1B 3
2OE 4
2A 5
2B 6
7
14
13 4OE
12 4A
11 4B
10 3OE
9 3A
8
DBQ PACKAGE
(TOP VIEW)
NC 1
1OE 2
1A 3
1B 4
2OE 5
2A 6
2B 7
GND 8
16 VCC
15 4OE
14 4A
13 4B
12 3OE
11 3A
10 3B
9 NC
NC − No internal connection
description/ordering information
The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3125C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE, 3OE,
4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated
1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports.
When OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A
and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




 SN74CBT3125C
SN74CBT3125C
QUADRUPLE FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS122A − JULY 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74CBT3125CRGYR CU125C
SOIC − D
Tube
Tape and reel
SN74CBT3125CD
SN74CBT3125CDR
CBT3125C
−40°C to 85°C SSOP − DB
Tube
Tape and reel
SN74CBT3125CDB
SN74CBT3125CDBR
CU125C
SSOP (QSOP) − DBQ Tape and reel SN74CBT3125CDBQR CU125C
TSSOP − PW
Tube
Tape and reel
SN74CBT3125CPW
SN74CBT3125CPWR
CU125C
TVSOP − DGV
Tape and reel SN74CBT3125CDGVR CU125C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
INPUT
OE
L
H
FUNCTION TABLE
(each bus switch)
INPUT/OUTPUT
A
FUNCTION
B
A port = B port
Z
Disconnect
logic diagram (positive logic)
2
1A
1
1OE
3
SW
1B
5
2A
4
2OE
6
SW
2B
9
3A
10
3OE
8
SW
3B
12
4A
13
4OE
11
SW
4B
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74CBT3125C
SN74CBT3125C
QUADRUPLE FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS122A − JULY 2003 − REVISED OCTOBER 2003
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN
EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH High-level control input voltage
2 5.5 V
VIL Low-level control input voltage
0 0.8 V
VI/O Data input/output voltage
0 5.5 V
TA Operating free-air temperature
−40 85 °C
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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