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BUS SWITCH. SN74CBT3126 Datasheet

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BUS SWITCH. SN74CBT3126 Datasheet






SN74CBT3126 SWITCH. Datasheet pdf. Equivalent




SN74CBT3126 SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3126

Description

QUADRUPLE FET BUS SWITCH



Feature


SN74CBT3126 QUADRUPLE FET BUS SWITCH D Standard ’126-Type Pinout (D, DB, DGV , and PW Packages) D 5-Ω Switch Connec tion Between Two Ports SCDS020K − MA Y 1995 − REVISED OCTOBER 2003 D TTL-C ompatible Input Levels D Latch-Up Perfo rmance Exceeds 250 mA Per JESD 17 D, D B, DGV, OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1B 3 2OE 4 2A 5 2B 6 GND 7 14 VC C 13 4OE 12 4A 11 4B 10 3.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3126 Datasheet


Texas Instruments SN74CBT3126

SN74CBT3126; OE 9 3A 8 3B RGY PACKAGE (TOP VIEW) 1O E VCC 1 1A 2 1B 3 2OE 4 2A 5 2B 6 7 1 4 13 4OE 12 4A 11 4B 10 3OE 9 3A 8 DBQ PACKAGE (TOP VIEW) NC 1 1OE 2 1A 3 1B 4 2OE 5 2A 6 2B 7 GND 8 16 VCC 15 4OE 14 4A 13 4B 12 3OE 11 3A 10 3B 9 NC N C − No internal connection GND 3B d escription/ordering information The SN7 4CBT3126 quadruple FET bus switch featu res independent line.


Texas Instruments SN74CBT3126

switches. Each switch is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance s tate during power up or power down, OE should be tied to GND through a pulldow n resistor; the minimum value of the re sistor is determined by the current-sou rcing capability of the driver. ORDERI NG INFORMATION TA PACKAGE† ORDERAB LE PART NUMBER TOP-.


Texas Instruments SN74CBT3126

SIDE MARKING QFN − RGY Tape and reel SN74CBT3126RGYR CU126 SOIC − D Tub e Tape and reel SN74CBT3126D SN74CBT31 26DR CBT3126 SSOP − DB Tape and re el −40°C to 85°C SSOP (QSOP) − DBQ Tape and reel SN74CBT3126DBR CU126 SN74CBT3126DBQR CU126 TSSOP − PW T ube Tape and reel SN74CBT3126PW SN74CB T3126PWR CU126 TVSOP − DGV Tape an d reel SN74CBT3126DGVR CU126 † Pa.

Part

SN74CBT3126

Description

QUADRUPLE FET BUS SWITCH



Feature


SN74CBT3126 QUADRUPLE FET BUS SWITCH D Standard ’126-Type Pinout (D, DB, DGV , and PW Packages) D 5-Ω Switch Connec tion Between Two Ports SCDS020K − MA Y 1995 − REVISED OCTOBER 2003 D TTL-C ompatible Input Levels D Latch-Up Perfo rmance Exceeds 250 mA Per JESD 17 D, D B, DGV, OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1B 3 2OE 4 2A 5 2B 6 GND 7 14 VC C 13 4OE 12 4A 11 4B 10 3.
Manufacture

Texas Instruments

Datasheet
Download SN74CBT3126 Datasheet




 SN74CBT3126
SN74CBT3126
QUADRUPLE FET BUS SWITCH
D Standard ’126-Type Pinout (D, DB, DGV,
and PW Packages)
D 5-Ω Switch Connection Between Two Ports
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
D TTL-Compatible Input Levels
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
2OE 4
2A 5
2B 6
GND 7
14 VCC
13 4OE
12 4A
11 4B
10 3OE
9 3A
8 3B
RGY PACKAGE
(TOP VIEW)
1
1A 2
1B 3
2OE 4
2A 5
2B 6
7
14
13 4OE
12 4A
11 4B
10 3OE
9 3A
8
DBQ PACKAGE
(TOP VIEW)
NC 1
1OE 2
1A 3
1B 4
2OE 5
2A 6
2B 7
GND 8
16 VCC
15 4OE
14 4A
13 4B
12 3OE
11 3A
10 3B
9 NC
NC − No internal connection
description/ordering information
The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74CBT3126RGYR CU126
SOIC − D
Tube
Tape and reel
SN74CBT3126D
SN74CBT3126DR
CBT3126
SSOP − DB
Tape and reel
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel
SN74CBT3126DBR CU126
SN74CBT3126DBQR CU126
TSSOP − PW
Tube
Tape and reel
SN74CBT3126PW
SN74CBT3126PWR
CU126
TVSOP − DGV
Tape and reel SN74CBT3126DGVR CU126
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
Disconnect
H
A=B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated
1




 SN74CBT3126
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
1A
3
1B
1
1OE
5
2A
6
2B
4
2OE
9
3A
8
3B
10
3OE
12
4A
13
4OE
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
11
4B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage
VIH High-level control input voltage
VIL Low-level control input voltage
TA Operating free-air temperature
4 5.5 V
2
V
0.8 V
−40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74CBT3126
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPMAX UNIT
VIK
VCC = 4.5 V,
II = −18 mA
−1.2 V
II
VCC = 5.5 V,
VI = 5.5 V or GND
±1 μA
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
3 μA
ΔICC‡ Control inputs VCC = 5.5 V,
One input at 3.4 V, Other inputs at VCC or GND
2.5 mA
Ci
Control inputs VI = 3 V or 0
3
pF
Cio(OFF)
VO = 3 V or 0,
OE = GND
4
pF
VCC = 4 V,
TYP at VCC = 4 V,
VI = 2.4 V,
II = 15 mA
16
22
ron§
VCC = 4.5 V
VI = 0
II = 64 mA
II = 30 mA
5
7
Ω
5
7
VI = 2.4 V,
II = 15 mA
10
15
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V
MIN MAX
VCC = 5 V
± 0.5 V
MIN MAX
UNIT
tpd¶
A or B
B or A
0.35
0.25 ns
ten
OE
A or B
5.4 1.6 5.1 ns
tdis
OE
A or B
5
1 4.5 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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