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BUS SWITCH. SN74CBT3245C Datasheet

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BUS SWITCH. SN74CBT3245C Datasheet







SN74CBT3245C SWITCH. Datasheet pdf. Equivalent




SN74CBT3245C SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT3245C

Description

8-BIT FET BUS SWITCH

Manufacture

Texas Instruments

Datasheet
Download SN74CBT3245C Datasheet


Texas Instruments SN74CBT3245C

SN74CBT3245C; SN74CBT3245C 8ĆBIT FET BUS SWITCH 5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTE CTION SCDS131A − SEPTEMBER 2003 − R EVISED OCTOBER 2003 D Undershoot Prote ction for Off-Isolation on A and B Port s Up To −2 V D Bidirectional Data Flo w, With Near-Zero Propagation Delay D L ow ON-State Resistance (ron) Characteri stics (ron = 3 Ω Typical) D Low Input /Output Capacitance Minimizes .


Texas Instruments SN74CBT3245C

Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical) D Data and Control In puts Provide Undershoot Clamp Diodes D Low Power Consumption (ICC = 3 µA Max) D VCC Operating Range From 4 V to 5.5 V D Data I/Os Support 0 to 5-V Signalin g Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2 .5-V, 3.3-V, 5-V) D Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Out puts D Ioff Support.


Texas Instruments SN74CBT3245C

s Partial-Power-Down Mode Operation D La tch-Up Performance Exceeds 100 mA Per J ESD 78, Class II D ESD Performance Test ed Per JESD 22 − 2000-V Human-Body Mo del (A114-B, Class II) − 1000-V Charg ed-Device Model (C101) D Supports Both Digital and Analog Applications: USB In terface, Memory Interleaving, Bus Isola tion, Low-Distortion Signal Gating DB, DBQ, DGV, DW, OR PW P.



Part

SN74CBT3245C

Description

8-BIT FET BUS SWITCH

Manufacture

Texas Instruments

Datasheet
Download SN74CBT3245C Datasheet




 SN74CBT3245C
SN74CBT3245C
8ĆBIT FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (ron)
Characteristics (ron = 3 Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5.5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(ICC = 3 µA Max)
D VCC Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
NC 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
NC − No internal connection
1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
10
20
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11
NC − No internal connection
description/ordering information
The SN74CBT3245C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3245C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3245C is organized as an 8-bit bus switch with a single output-enable (OE) input. When OE is
low, the bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between
ports. When OE is high, the bus switch is OFF, and the high-impedance state exists between the A and B ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1





 SN74CBT3245C
SN74CBT3245C
8ĆBIT FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74CBT3245CRGYR CU245C
SOIC − DW
Tube
Tape and reel
SN74CBT3245CDW
SN74CBT3245CDWR
CBT3245C
−40°C to 85°C SSOP − DB
Tube
Tape and reel
SN74CBT3245CDB
SN74CBT3245CDBR
CU245C
SSOP (QSOP) − DBQ Tape and reel SN74CBT3245CDBQR CBT3245C
TSSOP − PW
Tube
Tape and reel
SN74CBT3245CPW
SN74CBT3245CPWR
CU245C
TVSOP − DGV
Tape and reel SN74CBT3245CDGVR CU245C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
INPUT
OE
L
H
FUNCTION TABLE
INPUT/OUTPUT
A
FUNCTION
B
A port = B port
Z
Disconnect
logic diagram (positive logic)
2
A1
18
SW
B1
9
A8
19
OE
11
SW
B8
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 SN74CBT3245C
SN74CBT3245C
8ĆBIT FET BUS SWITCH
5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTION
SCDS131A − SEPTEMBER 2003 − REVISED OCTOBER 2003
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN
EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 5): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH High-level control input voltage
2 5.5 V
VIL Low-level control input voltage
0 0.8 V
VI/O Data input/output voltage
0 5.5 V
TA Operating free-air temperature
−40 85 °C
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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