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FET MULTIPLEXER/DEMULTIPLEXER. SN74CBT3257D Datasheet

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FET MULTIPLEXER/DEMULTIPLEXER. SN74CBT3257D Datasheet






SN74CBT3257D MULTIPLEXER/DEMULTIPLEXER. Datasheet pdf. Equivalent




SN74CBT3257D MULTIPLEXER/DEMULTIPLEXER. Datasheet pdf. Equivalent





Part

SN74CBT3257D

Description

4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

Manufacture

Texas Instruments

Datasheet
Download SN74CBT3257D Datasheet


Texas Instruments SN74CBT3257D

SN74CBT3257D; SN74CBT3257 4-BIT 1-OF-2 FET MULTIPLEXER /DEMULTIPLEXER D 5-Ω Switch Connectio n Between Two Ports D, DB, DBQ, OR PW PACKAGE (TOP VIEW) S1 1B1 2 1B2 3 1A 4 2B1 5 2B2 6 2A 7 GND 8 16 VCC 15 OE 1 4 4B1 13 4B2 12 4A 11 3B1 10 3B2 9 3A SCDS017M − MAY 1995 − REVISED JANUA RY 2004 D TTL-Compatible Input Levels R GY PACKAGE (TOP VIEW) VCC S 1 1B1 2 1B2 3 1A 4 2B1 5 2B2 6 .


Texas Instruments SN74CBT3257D

2A 7 8 16 15 OE 14 4B1 13 4B2 12 4A 11 3B1 10 3B2 9 3A GND description/orde ring information The SN74CBT3257 is a 4 -bit 1-of-2 high-speed TTL-compatible F ET multiplexer/demultiplexer. The low o n-state resistance of the switch allows connections to be made with minimal pr opagation delay. Output-enable (OE) and select-control (S) inputs select the a ppropriate B1 and .


Texas Instruments SN74CBT3257D

B2 outputs for the A-input data. ORDERI NG INFORMATION TA PACKAGE† ORDERAB LE PART NUMBER TOP-SIDE MARKING QFN RGY Tape and reel SN74CBT3257RGYR C U257 SOIC − D Tube Tape and reel S N74CBT3257D SN74CBT3257DR CBT3257 − 40°C to 85°C SSOP − DB Tape and re el SSOP (QSOP) − DBQ Tape and reel SN74CBT3257DBR CU257 SN74CBT3257DBQR CU 257 TSSOP − PW Tube Tape and r.



Part

SN74CBT3257D

Description

4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

Manufacture

Texas Instruments

Datasheet
Download SN74CBT3257D Datasheet




 SN74CBT3257D
SN74CBT3257
4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
D 5-Ω Switch Connection Between Two Ports
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
S1
1B1 2
1B2 3
1A 4
2B1 5
2B2 6
2A 7
GND 8
16 VCC
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
9 3A
SCDS017M − MAY 1995 − REVISED JANUARY 2004
D TTL-Compatible Input Levels
RGY PACKAGE
(TOP VIEW)
1
1B1 2
1B2 3
1A 4
2B1 5
2B2 6
2A 7
8
16
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
9
description/ordering information
The SN74CBT3257 is a 4-bit 1-of-2 high-speed TTL-compatible FET multiplexer/demultiplexer. The low
on-state resistance of the switch allows connections to be made with minimal propagation delay.
Output-enable (OE) and select-control (S) inputs select the appropriate B1 and B2 outputs for the A-input data.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74CBT3257RGYR CU257
SOIC − D
Tube
Tape and reel
SN74CBT3257D
SN74CBT3257DR
CBT3257
−40°C to 85°C SSOP − DB
Tape and reel
SSOP (QSOP) − DBQ Tape and reel
SN74CBT3257DBR CU257
SN74CBT3257DBQR CU257
TSSOP − PW
Tube
Tape and reel
SN74CBT3257PW
SN74CBT3257PWR
CU257
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
S
FUNCTION
L
L A port = B1 port
L
H A port = B2 port
H
X
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2004, Texas Instruments Incorporated
1





 SN74CBT3257D
SN74CBT3257
4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS017M − MAY 1995 − REVISED JANUARY 2004
logic diagram (positive logic)
4
1A
7
2A
9
3A
12
4A
1
S
15
OE
2
1B1
3
1B2
5
2B1
6
2B2
11
3B1
10
3B2
14
4B1
13
4B2
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 SN74CBT3257D
SN74CBT3257
4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS017M − MAY 1995 − REVISED JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH High-level control input voltage
2
V
VIL Low-level control input voltage
0.8 V
TA Operating free-air temperature
−40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPMAX UNIT
VIK
II
ICC
ΔICC§
Ci
Cio(OFF)
Control inputs
Control inputs
A port
B port
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VI = 3 V or 0
VO = 3 V or 0,
II = −18 mA
VI = 5.5 V or GND
IO = 0,
One input at 3.4 V,
VI = VCC or GND
Other inputs at VCC or GND
OE = VCC
−1.2 V
±1 μA
3 μA
2.5 mA
3.5
pF
6.5
pF
4
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
II = 15 mA
14
20
ron¶
VCC = 4.5 V
VI = 0
II = 64 mA
II = 30 mA
5
7Ω
5
7
VI = 2.4 V,
II = 15 mA
10
15
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) terminals.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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