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BUS SWITCH. SN74CBT386 Datasheet

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BUS SWITCH. SN74CBT386 Datasheet






SN74CBT386 SWITCH. Datasheet pdf. Equivalent




SN74CBT386 SWITCH. Datasheet pdf. Equivalent





Part

SN74CBT386

Description

10-BIT FET BUS SWITCH

Manufacture

Texas Instruments

Datasheet
Download SN74CBT386 Datasheet


Texas Instruments SN74CBT386

SN74CBT386; SN74CBT3861 10-BIT FET BUS SWITCH D 5- Switch Connection Between Two Ports D TTL-Compatible Input Levels D Latch-U p Performance Exceeds 250 mA Per JESD 1 7 description The SN74CBT3861 provides ten bits of high-speed TTL-compatible b us switching. The low on-state resistan ce of the switch allows connections to be made with minimal propagation delay. The device is organ.


Texas Instruments SN74CBT386

ized as one 10-bit switch with a single output-enable (OE) input. When OE is lo w, the switch is on, and port A is conn ected to port B. When OE is high, the s witch is open, and the high-impedance s tate exists between the two ports. SCD S061D – APRIL 1998 – REVISED OCTOBE R 2000 DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) NC 1 A1 2 A2 3 A3 4 A4 5 A5 6 A 6 7 A7 8 A8 9 A9 10 A1.


Texas Instruments SN74CBT386

0 11 GND 12 24 VCC 23 OE 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 15 B8 14 B9 13 B10 NC – No internal connection ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC – DW Tube SN74CBT3861DW Tap e and reel SN74CBT3861DWR CBT3861 – 40°C to 85°C SSOP (QSOP) – DBQ Tape and reel SN74CBT3861DBQR CBT3861 TSSO P – PW Tape and reel SN74CBT3.



Part

SN74CBT386

Description

10-BIT FET BUS SWITCH

Manufacture

Texas Instruments

Datasheet
Download SN74CBT386 Datasheet




 SN74CBT386
SN74CBT3861
10-BIT FET BUS SWITCH
D 5-Switch Connection Between Two Ports
D TTL-Compatible Input Levels
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
description
The SN74CBT3861 provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as one 10-bit switch with
a single output-enable (OE) input. When OE is
low, the switch is on, and port A is connected to
port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
NC 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A9 10
A10 11
GND 12
24 VCC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
NC – No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC – DW
Tube
SN74CBT3861DW
Tape and reel SN74CBT3861DWR
CBT3861
–40°C to 85°C SSOP (QSOP) – DBQ Tape and reel SN74CBT3861DBQR CBT3861
TSSOP – PW
Tape and reel SN74CBT3861PWR
CU861
TVSOP – DGV
Tape and reel SN74CBT3861DGVR CU861
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
OE
FUNCTION
L A port = B port
H
Disconnect
logic diagram (positive logic)
2
A1
22
B1
11
A10
13
B10
23
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
1





 SN74CBT386
SN74CBT3861
10-BIT FET BUS SWITCH
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage
4 5.5 V
VIH High-level control input voltage
2
V
VIL Low-level control input voltage
0.8 V
TA Operating free-air temperature
–40
85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP‡ MAX UNIT
VIK
VCC = 4.5 V,
II = –18 mA
–1.2 V
II
VCC = 5.5 V,
VI = 5.5 V or GND
±1 µA
ICC
VCC = 5.5 V,
ICC§ Control inputs VCC = 5.5 V,
IO = 0,
One input at 3.4 V,
VI = VCC or GND
Other inputs at VCC or GND
3 µA
2.5 mA
Ci
Control inputs VI = 3 V or 0
3
pF
Cio(OFF)
VO = 3 V or 0,
OE = VCC
5
pF
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
II = 15 mA
14
22
ron¶
VCC = 4.5 V
VI = 0
II = 64 mA
II = 30 mA
5
7
5
7
VI = 2.4 V,
II = 15 mA
10
15
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 SN74CBT386
SN74CBT3861
10-BIT FET BUS SWITCH
SCDS061D – APRIL 1998 – REVISED OCTOBER 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V
MIN MAX
VCC = 5 V
± 0.5 V
MIN MAX
UNIT
tpd†
A or B
B or A
0.35
0.25 ns
ten
OE
A or B
8.1 3.8 7.5 ns
tdis
OE
A or B
6.3 3.4 6.6 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 S1
500
7V
Open
GND
LOAD CIRCUIT
Input
1.5 V
3V
1.5 V
0V
tPLH
Output
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPHL
1.5 V
VOH
VOL
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
Output
Control
1.5 V
3V
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZL
Output
Waveform 2
S1 at Open
(see Note B)
tPZH
1.5 V
1.5 V
tPLZ
3.5 V
VOL + 0.3 V
VOL
tPHZ
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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