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CLOCK SOURCE. ICS557GI-03LF Datasheet

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CLOCK SOURCE. ICS557GI-03LF Datasheet






ICS557GI-03LF SOURCE. Datasheet pdf. Equivalent




ICS557GI-03LF SOURCE. Datasheet pdf. Equivalent





Part

ICS557GI-03LF

Description

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE



Feature


2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE DATASHEET ICS557-03 Description The IC S557-03 is a spread spectrum clock gene rator that supports PCI-Express Gen 1 a nd Ethernet requirements. The device is used for PC or embedded systems to sub stantially reduce electromagnetic inter ference (EMI). The device provides two differential (HCSL) spread spectrum out puts. The spread t.
Manufacture

Renesas

Datasheet
Download ICS557GI-03LF Datasheet


Renesas ICS557GI-03LF

ICS557GI-03LF; ype and amount are configured via select pin. Using IDT’s patented Phase-Lock ed Loop (PLL) techniques, the device ta kes a 25 MHz crystal input and produces two pairs of differential outputs at 2 5 MHz, 100 MHz, 125 MHz or 200 MHz cloc k frequencies for HCSL, and 25 MHz or 1 00 MHz for LVDS. Features • Packaged in 16-pin TSSOP • RoHS 5 (green) or RoHS 6 (green and lead f.


Renesas ICS557GI-03LF

ree) compliant packaging • Supports HC SL or LVDS output levels • Operating voltage of 3.3 V • Input frequency of 25 MHz • Jitter 60 ps (cycle-to-cycl e) • Spread Spectrum capability • I ndustrial and commercial temperature ra nges • For PCIe Gen2 applications, se e the 5V41065 • For PCIe Gen3 applica tions, see the 5V41235 Block Diagram V DD 2 SS1:SS0 2 S1:S0 2 Control L.


Renesas ICS557GI-03LF

ogic Phase Lock Loop X1/ICLK 25 MHz cr ystal or clock X2 Clock Buffer/ Crysta l Oscillator Optional tuning crystal c apacitors 2 GND OE CLK0 CLK0 CLK1 C LK1 Rr(IREF) IDT® 2 OUTPUT PCI-EXPRES S GEN1 CLOCK SOURCE 1 ICS557-03 REV U 112111 ICS557-03 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE PCIE SSCG Pin Assi gnment S0 1 S1 2 SS0 3 X1/ICLK 4 X2 5 OE 6 GNDXD 7 SS1 8 .

Part

ICS557GI-03LF

Description

2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE



Feature


2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE DATASHEET ICS557-03 Description The IC S557-03 is a spread spectrum clock gene rator that supports PCI-Express Gen 1 a nd Ethernet requirements. The device is used for PC or embedded systems to sub stantially reduce electromagnetic inter ference (EMI). The device provides two differential (HCSL) spread spectrum out puts. The spread t.
Manufacture

Renesas

Datasheet
Download ICS557GI-03LF Datasheet




 ICS557GI-03LF
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
DATASHEET
ICS557-03
Description
The ICS557-03 is a spread spectrum clock generator that
supports PCI-Express Gen 1 and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference (EMI).
The device provides two differential (HCSL) spread
spectrum outputs. The spread type and amount are
configured via select pin. Using IDT’s patented
Phase-Locked Loop (PLL) techniques, the device takes a
25 MHz crystal input and produces two pairs of differential
outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock
frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.
Features
Packaged in 16-pin TSSOP
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
Supports HCSL or LVDS output levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Jitter 60 ps (cycle-to-cycle)
Spread Spectrum capability
Industrial and commercial temperature ranges
For PCIe Gen2 applications, see the 5V41065
For PCIe Gen3 applications, see the 5V41235
Block Diagram
VDD
2
SS1:SS0
2
S1:S0
2
Control
Logic
Phase Lock Loop
X1/ICLK
25 MHz
crystal or clock X2
Clock
Buffer/
Crystal
Oscillator
Optional tuning crystal
capacitors
2
GND
OE
CLK0
CLK0
CLK1
CLK1
Rr(IREF)
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
1
ICS557-03 REV U 112111




 ICS557GI-03LF
ICS557-03
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Pin Assignment
S0 1
S1 2
SS0 3
X1/ICLK 4
X2 5
OE 6
GNDXD 7
SS1 8
16 VDDXD
15 CLK0
14 CLK0
13 GNDODA
12 VDDODA
11 CLK1
10
CLK1
9
IREF
16-pin (173 mil) TSSOP
Pin Descriptions
Output Select Table 1 (MHz)
S1 S0 CLK(1:0), CLK(1:0)
0
0
25M
0
1
100M
1
0
125M
1
1
200M
Spread Selection Table 2
SS1 SS0 Spread%
0
0
No Spread
0
1
Down -0.5
1
0
Down -0.75
1
1
No Spread
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
Pin
Type
Pin Description
Input Select pin 0. See Table1. Internal pull-up resistor.
Input Select pin 1. See Table 1. Internal pull-up resistor.
Input Spread Select pin 0. See Table 2. Internal pull-up resistor.
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output Crystal connection. Leave unconnected for clock input.
Input Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
Power Connect to ground.
Input Spread Select pin 1. See Table 2. Internal pull-up resistor.
Output Precision resistor attached to this pin is connected to the internal current
reference.
Output HCSL complimentary clock output 1.
Output HCSL true clock output 1.
Power Connect to voltage supply +3.3 V for output driver and analog circuits
Power Connect to ground.
Output HCSL complimentary clock output 0.
Output HCSL true clock output 0.
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
2
ICS557-03 REV U 112111




 ICS557GI-03LF
ICS557-03
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01 μF should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the ICS557-03 to
meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
CL= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (CL- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50Ω, then RR = 475Ω
(1%), providing IREF of 2.32 mA. The output current (IOH) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the ICS557-03
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-03 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
Output Structures
IREF
=2.3 mA
6*IREF
See Output Termination
RR 475Ω Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-03.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
3
ICS557-03 REV U 112111






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