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CLOCK SOURCE. 557M01LF Datasheet

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CLOCK SOURCE. 557M01LF Datasheet






557M01LF SOURCE. Datasheet pdf. Equivalent




557M01LF SOURCE. Datasheet pdf. Equivalent





Part

557M01LF

Description

PCI-EXPRESS GEN1 CLOCK SOURCE



Feature


PCI-EXPRESS GEN1 CLOCK SOURCE DATASHEET ICS557-01 Description The ICS557-01 i s a clock chip designed for use in PCI- Express Cards as a clock source. It pro vides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package. Using IDT’s patented Phase-Locked Lo op (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal .
Manufacture

Renesas

Datasheet
Download 557M01LF Datasheet


Renesas 557M01LF

557M01LF; Level) differential outputs at 100 MHz c lock frequency. LVDS signal levels can also be supported via an alternative te rmination scheme. Features • Support s PCI-ExpressTM HCSL Outputs 0.7 V curr ent mode differential pair • Supports LVDS Output Levels • Packaged in 8-p in SOIC • RoHS 5 (green) or RoHS 6 (g reen and lead free) compliant packaging • Operating voltage of 3..


Renesas 557M01LF

3 V • Low power consumption • Input frequency of 25 MHz • Short term jitt er 100 ps (peak-to-peak) • Output Ena ble via pin selection • Industrial te mperature range available • For PCIe Gen2 applications, see the 5V41064 • For PCIe Gen3 applications, see the 5V4 1234 Block Diagram VDD X1 25 MHz crys tal /clock X2 Clock Buffer/ Crystal Os cillator Phase Lock Loop Cryst.


Renesas 557M01LF

al Tuning Capacitors GND OE CLK CLK R R(IREF) IDT® PCI-EXPRESS GEN1 CLOCK S OURCE 1 ICS557-01 REV P 072512 ICS55 7-01 PCI-EXPRESS GEN1 CLOCK SOURCE Pin Assignment OE 1 X1 2 X2 3 GND 4 8 VDD 7 CLK 6 CLK 5 IREF 8 Pin (150 mil) SOIC PCIE Pin Descriptions Pin Number 1 Pin Name OE 2 X1 3 X2 4 GND 5 IREF 6 CLK 7 CLK 8 VDD Pin Type Pin Descr.

Part

557M01LF

Description

PCI-EXPRESS GEN1 CLOCK SOURCE



Feature


PCI-EXPRESS GEN1 CLOCK SOURCE DATASHEET ICS557-01 Description The ICS557-01 i s a clock chip designed for use in PCI- Express Cards as a clock source. It pro vides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package. Using IDT’s patented Phase-Locked Lo op (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal .
Manufacture

Renesas

Datasheet
Download 557M01LF Datasheet




 557M01LF
PCI-EXPRESS GEN1 CLOCK SOURCE
DATASHEET
ICS557-01
Description
The ICS557-01 is a clock chip designed for use in
PCI-Express Cards as a clock source. It provides a pair of
differential outputs at 100 MHz in a small 8-pin SOIC
package.
Using IDT’s patented Phase-Locked Loop (PLL)
techniques, the device takes a 25 MHz crystal input and
produces HCSL (Host Clock Signal Level) differential
outputs at 100 MHz clock frequency. LVDS signal levels can
also be supported via an alternative termination scheme.
Features
Supports PCI-ExpressTM HCSL Outputs
0.7 V current mode differential pair
Supports LVDS Output Levels
Packaged in 8-pin SOIC
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
Operating voltage of 3.3 V
Low power consumption
Input frequency of 25 MHz
Short term jitter 100 ps (peak-to-peak)
Output Enable via pin selection
Industrial temperature range available
For PCIe Gen2 applications, see the 5V41064
For PCIe Gen3 applications, see the 5V41234
Block Diagram
VDD
X1
25 MHz
crystal /clock
X2
Clock
Buffer/
Crystal
Oscillator
Phase Lock
Loop
Crystal Tuning Capacitors
GND
OE
CLK
CLK
RR(IREF)
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE
1
ICS557-01 REV P 072512




 557M01LF
ICS557-01
PCI-EXPRESS GEN1 CLOCK SOURCE
Pin Assignment
OE
1
X1
2
X2
3
GND 4
8 VDD
7 CLK
6 CLK
5 IREF
8 Pin (150 mil) SOIC
PCIE
Pin Descriptions
Pin
Number
1
Pin
Name
OE
2
X1
3
X2
4
GND
5
IREF
6
CLK
7
CLK
8
VDD
Pin
Type
Pin Description
Input Output Enable signal
(H = outputs are enabled, L = outputs are disabled/tristated).
Internal pull-up resistor.
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
XO Crystal Connection. Connect to a parallel mode crystal.
Leave floating if clock input.
Power Connect to ground.
Output A 475Ω precision resistor connected between this pin and ground
establishes the external reference current.
Output HCSL differential complementary clock output.
Output HCSL differential clock output.
Power Connect to +3.3 V.
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE
2
ICS557-01 REV P 072512




 557M01LF
ICS557-01
PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01 μF should be connected
between VDD and the ground plane (pin 4) as close to the
VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into IDT pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with
CL = 16 pF should be used. This crystal must have less than
300 ppm of error across temperature in order for the
ICS557-01 to meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
CL= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (CL- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50Ω, then RR = 475Ω
(1%), providing IREF of 2.32 mA. The output current (IOH) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the ICS557-01
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-01can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout Guidelines
section
Output Structures
IREF
=2.3 mA
6*IREF
See Output Termination
RR 475W Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-01.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE
3
ICS557-01 REV P 072512






Recommended third-party 557M01LF Datasheet






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