DatasheetsPDF.com

CLOCK MUX. 557GI06LF Datasheet

DatasheetsPDF.com

CLOCK MUX. 557GI06LF Datasheet






557GI06LF MUX. Datasheet pdf. Equivalent




557GI06LF MUX. Datasheet pdf. Equivalent





Part

557GI06LF

Description

2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX



Feature


2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX DATASHEET ICS557-06 Description The I CS557-06 is a two to four differential clock mux designed for use in PCI-Expre ss applications. The device selects one of the two differential HCSL input pai rs and fans out to four pairs of differ ential HCSL or LVDS outputs. Features • Packaged in 20-pin TSSOP • Pb (le ad) free packaging • O.
Manufacture

Renesas

Datasheet
Download 557GI06LF Datasheet


Renesas 557GI06LF

557GI06LF; perating voltage of 3.3 V • Low power consumption • Input differential cloc k of up to 200 MHz • Jitter 60 ps (cy cle-to-cycle) • Output-to-output skew of 50 ps • Available in industrial t emperature range (-40 to +85°C) • Fo r PCIe Gen2/3 applications, see the 5V4 1067A Block Diagram IN1 IN1 IN2 IN2 V DD 2 MUX 2 to 1 2 SEL GND PD OE Rr (IREF) CLKA CLKA CLKB CLKB CL.


Renesas 557GI06LF

KC CLKC CLKD CLKD IDT® 2 TO 4 DIFFEREN TIAL PCIE GEN1 CLOCK MUX 1 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFEREN TIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Pin Assignment SEL 1 VDDIN 2 IN1 3 IN1 4 PD 5 IN2 6 IN2 7 OE 8 GND 9 IREF 10 20 CLKA 1 9 CLKA 18 CLKB 17 CLKB 16 GND 1 5 VDD 14 CLKC 13 CLKC 12 CLKD 1 1 CLKD 20-pin (17.


Renesas 557GI06LF

3 mil) TSSOP Select Table SEL 0 1 Inp ut Pair selected IN2/ IN2 IN1/ IN1 Pin Descriptions Pin Pin Pin Name Typ e Pin Description 1 SEL Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ I N2. Internal pull-up resistor. 2 VDDI N Power Connect to +3.3 V. Supply volt age for Input clocks. 3 IN1 Input HC SL true input signal 1. 4 IN1 Input HCSL complimentary.

Part

557GI06LF

Description

2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX



Feature


2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX DATASHEET ICS557-06 Description The I CS557-06 is a two to four differential clock mux designed for use in PCI-Expre ss applications. The device selects one of the two differential HCSL input pai rs and fans out to four pairs of differ ential HCSL or LVDS outputs. Features • Packaged in 20-pin TSSOP • Pb (le ad) free packaging • O.
Manufacture

Renesas

Datasheet
Download 557GI06LF Datasheet




 557GI06LF
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
DATASHEET
ICS557-06
Description
The ICS557-06 is a two to four differential clock mux
designed for use in PCI-Express applications. The device
selects one of the two differential HCSL input pairs and fans
out to four pairs of differential HCSL or LVDS outputs.
Features
Packaged in 20-pin TSSOP
Pb (lead) free packaging
Operating voltage of 3.3 V
Low power consumption
Input differential clock of up to 200 MHz
Jitter 60 ps (cycle-to-cycle)
Output-to-output skew of 50 ps
Available in industrial temperature range (-40 to +85°C)
For PCIe Gen2/3 applications, see the 5V41067A
Block Diagram
IN1
IN1
IN2
IN2
VDD
2
MUX
2 to 1
2
SEL GND
PD
OE
Rr (IREF)
CLKA
CLKA
CLKB
CLKB
CLKC
CLKC
CLKD
CLKD
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
1
ICS557-06 REV M 070512




 557GI06LF
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
Pin Assignment
SEL
1
VDDIN
2
IN1
3
IN1
4
PD
5
IN2
6
IN2
7
OE
8
GND
9
IREF
10
20
CLKA
19
CLKA
18
CLKB
17
CLKB
16
GND
15
VDD
14
CLKC
13
CLKC
12
CLKD
11
CLKD
20-pin (173 mil) TSSOP
Select Table
SEL
0
1
Input Pair
selected
IN2/ IN2
IN1/ IN1
Pin Descriptions
Pin
Pin
Pin
Name
Type
Pin Description
1
SEL
Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
2
VDDIN
Power Connect to +3.3 V. Supply voltage for Input clocks.
3
IN1
Input HCSL true input signal 1.
4
IN1
Input HCSL complimentary input signal 1.
5
PD
Input Powers down the chip and tri-states outputs when low. Internal pull-up
6
IN2
Input HCSL true input signal 2.
7
IN2
Input HCSL complimentary input signal 2.
8
OE
Input Provides fast output on, tri-states output (High = enable outputs; Low =
disable). Internal pull-up resistor outputs.
9
GND
Power Connect to ground.
10
Rr(IREF) Output Precision resistor attached to this pin is connected to the internal current
11
CLKD
Output Differential Complimentary output clock D.
12
CLKD
Output Differential True output clock D.
13
CLKC
Output Differential Complimentary output clock C.
14
CLKC
Output Differential True output clock C.
15
VDDOUT Power Connect to +3.3 V. Supply Voltage for Output Clocks.
16
GND
Power Connect to ground.
17
CLKB
Output Differential Complimentary output clock B.
18
CLKB
Output Differential True output clock B.
19
CLKA
Output Differential Complimentary output clock A.
20
CLKA
Output Differential True output clock A.
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
2
ICS557-06 REV M 070512




 557GI06LF
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-06.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
Load Resistors RL
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-06
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-06 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
3
ICS557-06 REV M 070512






Recommended third-party 557GI06LF Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)