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2:1 MULTIPLEXER. ICS557GI-08LF Datasheet

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2:1 MULTIPLEXER. ICS557GI-08LF Datasheet






ICS557GI-08LF MULTIPLEXER. Datasheet pdf. Equivalent




ICS557GI-08LF MULTIPLEXER. Datasheet pdf. Equivalent





Part

ICS557GI-08LF

Description

2:1 MULTIPLEXER



Feature


2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN 1 DATASHEET ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip th at allows the user to select one of the two HCSL (Host Clock Signal Level) inp ut pairs and fans out to one pair of di fferential HCSL or LVDS outputs. This c hip is suited especially for PCI-Expres s applications, where there is a need t o select the PCI-E.
Manufacture

Renesas

Datasheet
Download ICS557GI-08LF Datasheet


Renesas ICS557GI-08LF

ICS557GI-08LF; xpress clock either locally from the PCI -E card or from the motherboard. Featu res • Packaged in 16-pin TSSOP • Pb (lead) free package • Operating volt age of 3.3 V • Low power consumption • Input clock frequency of up to 200 MHz • For PCIe Gen2/3 applications, s ee the 5V41068A Block Diagram VDD OE 3 IN1 IN1 CLK MUX IN2 2 to 1 I N2 CLK 3 SEL GND PD Rr (I.


Renesas ICS557GI-08LF

REF) IDT® 2:1 MULTIPLEXER CHIP FOR PCI -EXPRESS GEN1 1 ICS557-08 REV L 11211 1 ICS557-08 2:1 MULTIPLEXER CHIP FOR P CI-EXPRESS GEN1 PCIE MULTIPLEXER Pin Assignment VDD 1 IN1 2 IN1 3 PD 4 IN2 5 IN2 6 OE 7 GND 8 16 SEL 15 CLK 14 CLK 13 GND 12 GND 11 VDD 10 VDD 9 IREF 16-pin (173 mil) TSSOP Select Table SEL 0 1 Input Pair Selected IN2 / IN2 IN1/ IN1 Pin.


Renesas ICS557GI-08LF

Descriptions Pin Pin Name Pin Type Pi n Description 1 VDD Power Connect to +3.3 V. Supply voltage for Input clock s. 2 IN1 Input HCSL true input signa l 1. 3 IN1 Input HCSL complimentary input signal 1. 4 PD Input Powers do wn the chip and tri-states outputs when low. Internal pull-up 5 IN2 Input H CSL true input signal 2. 6 IN2 Input HCSL complimentar.

Part

ICS557GI-08LF

Description

2:1 MULTIPLEXER



Feature


2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN 1 DATASHEET ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip th at allows the user to select one of the two HCSL (Host Clock Signal Level) inp ut pairs and fans out to one pair of di fferential HCSL or LVDS outputs. This c hip is suited especially for PCI-Expres s applications, where there is a need t o select the PCI-E.
Manufacture

Renesas

Datasheet
Download ICS557GI-08LF Datasheet




 ICS557GI-08LF
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
DATASHEET
ICS557-08
Description
The ICS557-08 is a 2:1 multiplexer chip that allows the user
to select one of the two HCSL (Host Clock Signal Level)
input pairs and fans out to one pair of differential HCSL or
LVDS outputs. This chip is suited especially for
PCI-Express applications, where there is a need to select
the PCI-Express clock either locally from the PCI-E card or
from the motherboard.
Features
Packaged in 16-pin TSSOP
Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input clock frequency of up to 200 MHz
For PCIe Gen2/3 applications, see the 5V41068A
Block Diagram
VDD
OE
3
IN1
IN1
CLK
MUX
IN2
2 to 1
IN2
CLK
3
SEL GND
PD
Rr (IREF)
IDT® 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
1
ICS557-08 REV L 112111




 ICS557GI-08LF
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Pin Assignment
VDD 1
IN1 2
IN1 3
PD 4
IN2 5
IN2 6
OE 7
GND 8
16 SEL
15 CLK
14
CLK
13 GND
12 GND
11 VDD
10 VDD
9
IREF
16-pin (173 mil) TSSOP
Select Table
SEL
0
1
Input Pair Selected
IN2/ IN2
IN1/ IN1
Pin Descriptions
Pin Pin Name Pin Type
Pin Description
1
VDD
Power Connect to +3.3 V. Supply voltage for Input clocks.
2
IN1
Input HCSL true input signal 1.
3
IN1
Input HCSL complimentary input signal 1.
4
PD
Input Powers down the chip and tri-states outputs when low. Internal pull-up
5
IN2
Input HCSL true input signal 2.
6
IN2
Input HCSL complimentary input signal 2.
7
OE
Input Provides output or, tri-states output (High = enable outputs; Low = disable).
Internal pull-up resistor.
8
GND
Power Connect to ground.
9
IREF
Output Precision resistor attached to this pin is connected to the internal current
10
VDD
Power Connect to +3.3 V. Supply Voltage for Output Clocks.
11
VDD
Power Connect to +3.3 V. Supply Voltage for Output Clocks.
12
GND
Power Connect to ground.
13
GND
Power Connect to ground.
14
CLK
Output HCSL/LVDS Complimentary output clock .
15
CLK
Output HCSL/LVDS True output clock.
16
SEL
Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
IDT® 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
2
ICS557-08 REV L 112111




 ICS557GI-08LF
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-08 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-08.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pins as close to the
device as possible.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
Load Resistors RL
Since the clock outputs are open source outputs, 50Ω
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-08
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-08 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
IDT® 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
3
ICS557-08 REV L 112111






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