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UPSD3454 Dataheets PDF



Part Number UPSD3454
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description Fast Turbo 8032 MCU
Datasheet UPSD3454 DatasheetUPSD3454 Datasheet (PDF)

UPSD3422 UPSD3433 UPSD3434 UPSD3454 Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic Features ■ Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40 MHz (5 V) ) – JTAG debug and in-system programming t(s – 16-bit internal instruction path fetches c double-byte instruction in a single memory u cycle rod – Branch cache & 4 instruction prefetch P t(s) queue – Dual XDATA pointers with automatic te c increment and decrem.

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UPSD3422 UPSD3433 UPSD3434 UPSD3454 Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic Features ■ Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40 MHz (5 V) ) – JTAG debug and in-system programming t(s – 16-bit internal instruction path fetches c double-byte instruction in a single memory u cycle rod – Branch cache & 4 instruction prefetch P t(s) queue – Dual XDATA pointers with automatic te c increment and decrement le du – Compatible with 3rd party 8051 tools so ro ■ Dual Flash memories with memory b P management - O te – Place either memory into 8032 program ) le address space or data address space t(s o – READ-while-WRITE operation for ins application programming and EEPROM c b emulation du O – Single voltage program and erase ro ) - – 100 000 guaranteed erase cycles, 15-year P t(s retention te c ■ Clock, reset, and power supply management le u – Flexible 8-level CPU clock divider register so rod – Normal, Idle, and power-down modes – Power-on-reset and low-voltage-reset b P supervisor O te – Programmable watchdog timer le ■ Programmable logic, general purpose so – 16 macrocells for logic applications (e.g., b shifters, state machines, chip-selects, glueO logic to keypads, and LCDs) LQFP52 (T), 52-lead, thin, quad, flat LQFP80 (U), 80-lead, thin, quad, flat ■ Communication interfaces – USB v2.0 Full Speed (12Mbps) – 10 endpoint pairs (In/Out), each endpoint with 64-byte FIFO (supports Control, Intr, and Bulk transfer types) – I2C Master/Slave controller, 833kHz – SPI Master controller, 10MHz – Two UARTs with independent baud rate – IrDA potocol: up to 115 kbaud – Up to 46 I/O, 5 V tolerant uPSD34xxV ■ Timers and interrupts – Three 8032 standard 16-bit timers – Programmable counter array (PCA), six 16bit modules for PWM, CAPCOM, and timers – 8/10/16-bit PWM operation – 12 Interrupt sources with two external interrupt pins ■ Packages – ECOPACK® compliant Table 1. Device summary Reference Part number uPSD3422 UPSD3422E, UPSD3422EV uPSD3433E UPSD3433E, UPSD3433EV uPSD3434 UPSD3434E, UPSD3434EV ■ A/D converter – Eight channels, 10-bit resolution, 6 µs uPSD3454 UPSD3454E, UPSD3454EV ■ Operating voltage source (±10%) – 5 V devices: 5.0 V and 3.3 V sources – 3.3 V devices: 3.3 V source January 2009 Rev 5 1/300 www.st.com 1 Contents Contents UPSD3422, UPSD3433, UPSD3434, UPSD3454 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ) 4.1 Internal memory (MCU module, standard 8032 memory: t(s DATA, IDATA, SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 c 4.1.1 DATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 du 4.1.2 IDATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ro ) 4.1.3 SFR memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 P t(s 4.2 External memory (PSD module: program memory, data memory) . . . . . 31 lete uc 4.2.1 Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 so rod 4.2.2 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 b P 4.2.3 Memory placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ) - O lete 5 8032 MCU core performance enhancements . . . . . . . . . . . . . . . . . . . . 33 t(s so 5.1 Pre-fetch queue (PFQ) and branch cache (BC) . . . . . . . . . . . . . . . . . . . . 34 uc Ob 5.2 PFQ example, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 rod - 5.3 Aggregate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 te P ct(s) 6 MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 sole rodu 7 8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 b P 7.1 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 O te7.2 Data pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ole7.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Obs 7.4 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 B register (B) . . .


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