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8032 MCU. UPSD3433EV Datasheet

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8032 MCU. UPSD3433EV Datasheet






UPSD3433EV MCU. Datasheet pdf. Equivalent




UPSD3433EV MCU. Datasheet pdf. Equivalent





Part

UPSD3433EV

Description

Fast Turbo 8032 MCU



Feature


UPSD3422 UPSD3433 UPSD3434 UPSD3454 Turb o Plus series Fast Turbo 8032 MCU with USB and programmable logic Features โ –  Fast 8-bit Turbo 8032 MCU, 40 MHz โ €“ Advanced core, 4-clocks per instruct ion โ€“ 10 MIPs peak performance at 40 MHz (5 V) ) โ€“ JTAG debug and in-syst em programming t(s โ€“ 16-bit internal instruction path fetches c double-byte instruction in a single memo.
Manufacture

STMicroelectronics

Datasheet
Download UPSD3433EV Datasheet


STMicroelectronics UPSD3433EV

UPSD3433EV; ry u cycle rod โ€“ Branch cache & 4 inst ruction prefetch P t(s) queue โ€“ Dual XDATA pointers with automatic te c incr ement and decrement le du โ€“ Compatibl e with 3rd party 8051 tools so ro โ–  D ual Flash memories with memory b P mana gement - O te โ€“ Place either memory i nto 8032 program ) le address space or data address space t(s o โ€“ READ-while -WRITE operation for ins appli.


STMicroelectronics UPSD3433EV

cation programming and EEPROM c b emulat ion du O โ€“ Single voltage program and erase ro ) - โ€“ 100 000 guaranteed er ase cycles, 15-year P t(s retention te c โ–  Clock, reset, and power supply ma nagement le u โ€“ Flexible 8-level CPU clock divider register so rod โ€“ Norma l, Idle, and power-down modes โ€“ Power -on-reset and low-voltage-reset b P sup ervisor O te โ€“ Programmable wa.


STMicroelectronics UPSD3433EV

tchdog timer le โ–  Programmable logic, general purpose so โ€“ 16 macrocells fo r logic applications (e.g., b shifters, state machines, chip-selects, glueO lo gic to keypads, and LCDs) LQFP52 (T), 52-lead, thin, quad, flat LQFP80 (U), 80-lead, thin, quad, flat โ–  Communic ation interfaces โ€“ USB v2.0 Full Spee d (12Mbps) โ€“ 10 endpoint pairs (In/Ou t), each endpoint with 64-by.

Part

UPSD3433EV

Description

Fast Turbo 8032 MCU



Feature


UPSD3422 UPSD3433 UPSD3434 UPSD3454 Turb o Plus series Fast Turbo 8032 MCU with USB and programmable logic Features โ –  Fast 8-bit Turbo 8032 MCU, 40 MHz โ €“ Advanced core, 4-clocks per instruct ion โ€“ 10 MIPs peak performance at 40 MHz (5 V) ) โ€“ JTAG debug and in-syst em programming t(s โ€“ 16-bit internal instruction path fetches c double-byte instruction in a single memo.
Manufacture

STMicroelectronics

Datasheet
Download UPSD3433EV Datasheet




 UPSD3433EV
UPSD3422 UPSD3433
UPSD3434 UPSD3454
Turbo Plus series
Fast Turbo 8032 MCU with USB and programmable logic
Features
โ–  Fast 8-bit Turbo 8032 MCU, 40 MHz
โ€“ Advanced core, 4-clocks per instruction
โ€“ 10 MIPs peak performance at 40 MHz (5 V)
) โ€“ JTAG debug and in-system programming
t(s โ€“ 16-bit internal instruction path fetches
c double-byte instruction in a single memory
u cycle
rod โ€“ Branch cache & 4 instruction prefetch
P t(s) queue
โ€“ Dual XDATA pointers with automatic
te c increment and decrement
le du โ€“ Compatible with 3rd party 8051 tools
so ro โ–  Dual Flash memories with memory
b P management
- O te โ€“ Place either memory into 8032 program
) le address space or data address space
t(s o โ€“ READ-while-WRITE operation for in-
s application programming and EEPROM
c b emulation
du O โ€“ Single voltage program and erase
ro ) - โ€“ 100 000 guaranteed erase cycles, 15-year
P t(s retention
te c โ–  Clock, reset, and power supply management
le u โ€“ Flexible 8-level CPU clock divider register
so rod โ€“ Normal, Idle, and power-down modes
โ€“ Power-on-reset and low-voltage-reset
b P supervisor
O te โ€“ Programmable watchdog timer
le โ–  Programmable logic, general purpose
so โ€“ 16 macrocells for logic applications (e.g.,
b shifters, state machines, chip-selects, glue-
O logic to keypads, and LCDs)
LQFP52 (T), 52-lead,
thin, quad, flat
LQFP80 (U), 80-lead,
thin, quad, flat
โ–  Communication interfaces
โ€“ USB v2.0 Full Speed (12Mbps)
โ€“ 10 endpoint pairs (In/Out), each endpoint
with 64-byte FIFO (supports Control, Intr,
and Bulk transfer types)
โ€“ I2C Master/Slave controller, 833kHz
โ€“ SPI Master controller, 10MHz
โ€“ Two UARTs with independent baud rate
โ€“ IrDA potocol: up to 115 kbaud
โ€“ Up to 46 I/O, 5 V tolerant uPSD34xxV
โ–  Timers and interrupts
โ€“ Three 8032 standard 16-bit timers
โ€“ Programmable counter array (PCA), six 16-
bit modules for PWM, CAPCOM, and
timers
โ€“ 8/10/16-bit PWM operation
โ€“ 12 Interrupt sources with two external
interrupt pins
โ–  Packages
โ€“ ECOPACKยฎ compliant
Table 1. Device summary
Reference
Part number
uPSD3422
UPSD3422E, UPSD3422EV
uPSD3433E
UPSD3433E, UPSD3433EV
uPSD3434
UPSD3434E, UPSD3434EV
โ–  A/D converter
โ€“ Eight channels, 10-bit resolution, 6 ยตs
uPSD3454
UPSD3454E, UPSD3454EV
โ–  Operating voltage source (ยฑ10%)
โ€“ 5 V devices: 5.0 V and 3.3 V sources
โ€“ 3.3 V devices: 3.3 V source
January 2009
Rev 5
1/300
www.st.com
1




 UPSD3433EV
Contents
Contents
UPSD3422, UPSD3433, UPSD3434, UPSD3454
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3
Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
) 4.1 Internal memory (MCU module, standard 8032 memory:
t(s DATA, IDATA, SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
c 4.1.1 DATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
du 4.1.2 IDATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ro ) 4.1.3 SFR memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
P t(s 4.2 External memory (PSD module: program memory, data memory) . . . . . 31
lete uc 4.2.1 Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
so rod 4.2.2 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
b P 4.2.3 Memory placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
) - O lete 5
8032 MCU core performance enhancements . . . . . . . . . . . . . . . . . . . . 33
t(s so 5.1 Pre-fetch queue (PFQ) and branch cache (BC) . . . . . . . . . . . . . . . . . . . . 34
uc Ob 5.2 PFQ example, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
rod - 5.3 Aggregate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
te P ct(s) 6
MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
sole rodu 7
8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
b P 7.1 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
O te7.2 Data pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ole7.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Obs 7.4 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5 B register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6 General purpose registers (R0 - R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7 Program status word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7.1 Carry flag (CY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7.2 Auxiliary carry flag (AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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 UPSD3433EV
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Contents
7.7.3
7.7.4
7.7.5
7.7.6
General purpose flag (F0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register bank select flags (RS1, RS0) . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overflow flag (OV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Parity flag (P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Special function registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
8032 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.2 Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
t(s) 9.3 Register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
c 9.4 Immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
du 9.5 External direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pro t(s) 9.6 External indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
te c 9.7 Indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
le du 9.8 Relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
so ro 9.9 Absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
b P 9.10 Long addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
) - O lete 9.11 Bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ct(s bso 10
UPSD34xx instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
rodu ) - O 11
Dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
P t(s 11.1 Data pointer control register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . 57
lete uc 11.2 Data pointer mode register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . 58
o d 11.2.1 Firmware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Obs Pro 12
Debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
olete 13
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Obs 13.1 Individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.1 External interrupts Int0 and Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.2 Timer 0 and 1 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1.3 Timer 2 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1.4 UART0 and UART1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1.5 SPI interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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