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8-Bit DAC. TLV5624ID Datasheet

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8-Bit DAC. TLV5624ID Datasheet






TLV5624ID DAC. Datasheet pdf. Equivalent




TLV5624ID DAC. Datasheet pdf. Equivalent





Part

TLV5624ID

Description

Low Power 8-Bit DAC



Feature


TLV5624 2.7ĆV TO 5.5ĆV LOW POWER 8ĆBI T DIGITALĆTOĆANALOG CONVERTER WITH IN TERNAL REFERENCE AND POWER DOWN SLAS235 B − JULY 1999 − REVISED APRIL 2004 features D 8-Bit Voltage Output DAC D Programmable Internal Reference D Progr ammable Settling Time: 1 µs in Fast Mo de, 3.5 µs in Slow Mode D Compatible W ith TMS320 and SPI Serial Ports D Di fferential Nonlinearity . . . <.
Manufacture

Texas Instruments

Datasheet
Download TLV5624ID Datasheet


Texas Instruments TLV5624ID

TLV5624ID; 0.2 LSB D Monotonic Over Temperature D OR DGK PACKAGE (TOP VIEW) DIN 1 SCLK 2 CS 3 FS 4 8 VDD 7 OUT 6 REF 5 AGND a pplications D Digital Servo Control Loo ps D Digital Offset and Gain Adjustment D Industrial Process Control D Machine and Motion Control Devices D Mass Stor age Devices description The TLV5624 is a 8-bit voltage output DAC with a flex ible 4-wire serial.


Texas Instruments TLV5624ID

interface. The serial interface allows glueless interface to TMS320 and SPI , QSPI, and Microwire serial port s. It is programmed with a 16-bit seria l string containing 4 control and 8 dat a bits. The resistor string output volt age is buffered by a x2 gain rail-to-ra il output buffer. The programmable sett ling time of the DAC allows the designe r to optimize speed vs p.


Texas Instruments TLV5624ID

ower dissipation. With its on-chip progr ammable precision voltage reference, th e TLV5624 simplifies overall system des ign. Because of its ability to source u p to 1 mA, the reference can also be us ed as a system reference. Implemented w ith a CMOS process, the device is desig ned for single supply operation from 2. 7 V to 5.5 V. It is available in an 8-p in SOIC and 8-pin .

Part

TLV5624ID

Description

Low Power 8-Bit DAC



Feature


TLV5624 2.7ĆV TO 5.5ĆV LOW POWER 8ĆBI T DIGITALĆTOĆANALOG CONVERTER WITH IN TERNAL REFERENCE AND POWER DOWN SLAS235 B − JULY 1999 − REVISED APRIL 2004 features D 8-Bit Voltage Output DAC D Programmable Internal Reference D Progr ammable Settling Time: 1 µs in Fast Mo de, 3.5 µs in Slow Mode D Compatible W ith TMS320 and SPI Serial Ports D Di fferential Nonlinearity . . . <.
Manufacture

Texas Instruments

Datasheet
Download TLV5624ID Datasheet




 TLV5624ID
TLV5624
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235B − JULY 1999 − REVISED APRIL 2004
features
D 8-Bit Voltage Output DAC
D Programmable Internal Reference
D Programmable Settling Time:
1 µs in Fast Mode,
3.5 µs in Slow Mode
D Compatible With TMS320 and SPISerial
Ports
D Differential Nonlinearity . . . <0.2 LSB
D Monotonic Over Temperature
D OR DGK PACKAGE
(TOP VIEW)
DIN 1
SCLK 2
CS 3
FS 4
8 VDD
7 OUT
6 REF
5 AGND
applications
D Digital Servo Control Loops
D Digital Offset and Gain Adjustment
D Industrial Process Control
D Machine and Motion Control Devices
D Mass Storage Devices
description
The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows
glueless interface to TMS320 and SPI, QSPI, and Microwireserial ports. It is programmed with a 16-bit
serial string containing 4 control and 8 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling
time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable
precision voltage reference, the TLV5624 simplifies overall system design.
Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in
an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial
temperature ranges.
TA
0°C to 70°C
−40°C to 85°C
AVAILABLE OPTIONS
PACKAGE
SOIC
(D)
TLV5624CD
TLV5624ID
MSOP
(DGK)
TLV5624CDGK
TLV5624IDGK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
WWW.TI.COM
Copyright 2002−2004, Texas Instruments Incorporated
1




 TLV5624ID
TLV5624
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235B − JULY 1999 − REVISED APRIL 2004
functional block diagram
REF
PGA With
Output Enable
Voltage
Bandgap
Power-On
Reset
Power
and Speed
Control
2
DIN
SCLK
CS
FS
Serial
Interface
and
Control
2
2-Bit
Control
Latch
8
8
8-Bit
DAC
Latch
TERMINAL
NAME
NO.
AGND
5
CS
3
DIN
1
FS
4
OUT
7
REF
6
SCLK
2
VDD
8
Terminal Functions
I/O/P
DESCRIPTION
P Ground
I Chip select. Digital input active low, used to enable/disable inputs
I Digital serial data input
I Frame sync input
O DAC A analog voltage output
I/O Analog reference voltage input/output
I Digital serial clock input
P Positive power supply
x2
OUT
2
WWW.TI.COM




 TLV5624ID
TLV5624
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235B − JULY 1999 − REVISED APRIL 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: TLV5624C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV5624I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX UNIT
Supply voltage, VDD
Power on reset, POR
VDD = 5 V
VDD = 3 V
4.5
5
5.5
V
2.7
3
3.3
0.55
2V
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REF terminal
Reference voltage, Vref to REF terminal
Load resistance, RL
Load capacitance, CL
Clock frequency, fCLK
Operating free-air temperature, TA
DVDD = 2.7 V
DVDD = 5.5 V
DVDD = 2.7 V
DVDD = 5.5 V
VDD = 5 V (see Note 1)
VDD = 3 V (see Note 1)
TLV5624C
TLV5624I
2
2.4
AGND
AGND
2
0
−40
V
2.048
1.024
0.6
1
VDD −1.5
VDD −1.5
100
20
70
85
V
V
V
k
pF
MHz
°C
NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD−0.4 V)/2 causes clipping of the transfer function. The output buffer of the
internal reference must be disabled, if an external reference is used.
WWW.TI.COM
3






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