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Digital-to-Analog Converter. TLV5628CN Datasheet

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Digital-to-Analog Converter. TLV5628CN Datasheet






TLV5628CN Converter. Datasheet pdf. Equivalent




TLV5628CN Converter. Datasheet pdf. Equivalent





Part

TLV5628CN

Description

Octal 8-Bit Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5628CN Datasheet


Texas Instruments TLV5628CN

TLV5628CN; TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-T O-ANALOG CONVERTERS D Eight 8-Bit Volt age Output DACs D 3-V Single Supply Ope ration D Serial Interface D High-Impeda nce Reference Inputs D Programmable for 1 or 2 Times Output Range D Simultaneo us Update Facility D Internal Power-On Reset D Low Power Consumption D Half-Bu ffered Output SLAS108A – JANUARY 199 5 – REVISED NOVEMBER.


Texas Instruments TLV5628CN

1995 DW OR N PACKAGE (TOP VIEW) DACB 1 DACA 2 GND 3 DATA 4 CLK 5 VDD 6 DACE 7 DACF 8 16 DACC 15 DACD 14 REF1 13 LD AC 12 LOAD 11 REF2 10 DACH 9 DACG appl ications D Programmable Voltage Sources D Digitally Controlled Amplifiers/Atte nuators D Mobile Communications D Autom atic Test Equipment D Process Monitorin g and Control D Signal Synthesis descri ption The TLV5628C.


Texas Instruments TLV5628CN

and TLV5628I are octal 8-bit voltage ou tput digital-to-analog converters (DACs ) with buffered reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times the reference voltages and GND, a nd the DACs are monotonic. The device i s simple to use, running from a single supply of 3 to 3.6 V. A power-on reset function is incorp.



Part

TLV5628CN

Description

Octal 8-Bit Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5628CN Datasheet




 TLV5628CN
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
D Eight 8-Bit Voltage Output DACs
D 3-V Single Supply Operation
D Serial Interface
D High-Impedance Reference Inputs
D Programmable for 1 or 2 Times Output
Range
D Simultaneous Update Facility
D Internal Power-On Reset
D Low Power Consumption
D Half-Buffered Output
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
DW OR N PACKAGE
(TOP VIEW)
DACB 1
DACA 2
GND 3
DATA 4
CLK 5
VDD 6
DACE 7
DACF 8
16 DACC
15 DACD
14 REF1
13 LDAC
12 LOAD
11 REF2
10 DACH
9 DACG
applications
D Programmable Voltage Sources
D Digitally Controlled Amplifiers/Attenuators
D Mobile Communications
D Automatic Test Equipment
D Process Monitoring and Control
D Signal Synthesis
description
The TLV5628C and TLV5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times
the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a
single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLV5628C and TLV5628I is over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1
or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs are updated simultaneously through control of the LDAC terminal.
The digital inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLV5628C is characterized for operation from 0°C to 70°C. The TLV5628I is characterized for operation
from – 40°C to 85°C. The TLV5628C and TLV5628I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(DW)
0°C to 70°C
TLV5628CDW
– 40°C to 85°C
TLV5628IDW
PLASTIC DIP
(N)
TLV5628CN
TLV5628IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
1





 TLV5628CN
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
functional block diagram
REF1
+
DAC
+
9
Latch
Latch 8
×2
REF2
+
DAC
+
Latch
Latch 8
×2
DAC
+
Latch
Latch 8
×2
CLK
DATA
LOAD
DAC
+
Latch
Latch 8
×2
Serial
Interface
LDAC
Power-On
Reset
Terminal Functions
TERMINAL
I/O
NAME NO.
DESCRIPTION
CLK
5 I Serial-interface clock, data enters on the negative edge
DACA
2 O DACA analog output
DACB
1 O DACB analog output
DACC
16 O DACC analog output
DACD
15 O DACD analog output
DACE
7 O DACE analog output
DACF
8 O DACF analog output
DACG
9 O DACG analog output
DACH
10 O DACH analog output
DATA
4 I Serial-interface digital data input
GND
3 I Ground return and reference terminal
LDAC
13 I DAC-update latch control
LOAD
12 I Serial-interface load control
REF1
14 I Reference voltage input to DACA
REF2
11 I Reference voltage input to DACB
VDD
6 I Positive supply voltage
DACA
DACD
DACE
DACH
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 TLV5628CN
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
detailed description
The TLV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is
maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon
the performance of the output buffer. Because the inputs are buffered, the DACs always present a
high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA
through DACD and REF2 is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:
+ VO(DACA|B|C|D|E|F|G|H) REF
CODE
256
) (1 RNG bit value)
where CODE is in the range of 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated and LOAD goes low. When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8 clock cycle periods are shown in Figures 3 and 4.
CLK
DATA
LOAD
tsu(DATA-CLK)
tv(DATA-CLK)
tsu(LOAD-CLK)
A2
A1
A0 RNG D7
D6
D5
D4
D2
D1
D0
tsu(CLK-LOAD)
tw(LOAD)
Figure 1. LOAD-Controlled Update (LDAC = Low)
DAC Update
CLK
DATA
LOAD
LDAC
tsu(DATA-CLK)
tv(DATA-CLK)
A2
A1
A0
RNG D7
D6
D5
D4
D2
D1
D0
tsu(LOAD – LDAC)
tw(LDAC)
Figure 2. LDAC-Controlled Update
DAC Update
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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