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Digital-to-Analog Converter. TLV5604ID Datasheet

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Digital-to-Analog Converter. TLV5604ID Datasheet







TLV5604ID Converter. Datasheet pdf. Equivalent




TLV5604ID Converter. Datasheet pdf. Equivalent





Part

TLV5604ID

Description

Quadruple Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5604ID Datasheet


Texas Instruments TLV5604ID

TLV5604ID; TLV5604 2.7-V TO 5.5-V 10-BIT 3-µS QUAD RUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS176B – DECEMBER 1997 – REVISED JULY 2002 D Four 10-Bit D/ A Converters D Programmable Settling Ti me of 3 µs or 9 µs Typ D TMS320, (Q)S PI, and Microwire Compatible Seri al Interface D Internal Power-On Reset D Low Power Consumption: 5.5 mW, Slow M ode – 5-V Supply 3.3 mW, Slow.


Texas Instruments TLV5604ID

Mode – 3-V Supply D Reference Input B uffers D Voltage Output Range . . . 2 the Reference Input Voltage D Monoton ic Over Temperature D Dual 2.7-V to 5.5 -V Supply (Separate Digital and Analog Supplies) description The TLV5604 is a quadruple 10-bit voltage output digital -to-analog converter (DAC) with a flexi ble 4-wire serial interface. The 4-wire serial interface all.


Texas Instruments TLV5604ID

ows glueless interface to TMS320, SPI, Q SPI, and Microwire serial ports. The TL V5604 is programmed with a 16-bit seria l word comprised of a DAC address, indi vidual DAC control bits, and a 10-bit D AC value. D Hardware Power Down (10 nA ) D Software Power Down (10 nA) D Simul taneous Update applications D Battery Powered Test Instruments D Digital Offs et and Gain Adjust.



Part

TLV5604ID

Description

Quadruple Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5604ID Datasheet




 TLV5604ID
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
D Four 10-Bit D/A Converters
D Programmable Settling Time
of 3 µs or 9 µs Typ
D TMS320, (Q)SPI, and Microwire
Compatible Serial Interface
D Internal Power-On Reset
D Low Power Consumption:
5.5 mW, Slow Mode – 5-V Supply
3.3 mW, Slow Mode – 3-V Supply
D Reference Input Buffers
D Voltage Output Range . . . 2 × the Reference
Input Voltage
D Monotonic Over Temperature
D Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
description
The TLV5604 is a quadruple 10-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5604 is
programmed with a 16-bit serial word comprised
of a DAC address, individual DAC control bits, and
a 10-bit DAC value.
D Hardware Power Down (10 nA)
D Software Power Down (10 nA)
D Simultaneous Update
applications
D Battery Powered Test Instruments
D Digital Offset and Gain Adjustment
D Industrial Process Controls
D Machine and Motion Control Devices
D Communications
D Arbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
DVDD 1
PD 2
LDAC 3
DIN 4
SCLK 5
CS 6
FS 7
DGND 8
16 AVDD
15 REFINAB
14 OUTA
13 OUTB
12 OUTC
11 OUTD
10 REFINCD
9 AGND
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND),
and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is
independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical
application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins
DVDD and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be
tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage then DACs C and D.
The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The
TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from
– 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1





 TLV5604ID
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B DECEMBER 1997 REVISED JULY 2002
TA
0°C to 70°C
40°C to 85°C
AVAILABLE OPTIONS
PACKAGE
SOIC
(D)
TSSOP
(PW)
TLV5604CD
TLV5604CPW
TLV5604ID
TLV5604IPW
functional block diagram
15
REFINAB
Power-On
Reset
DAC A
AVDD
16
DVDD
1
+
_
x2
14
OUTA
4 Serial 14
DIN
Input
Register
2
FS
SCLK
CS
7
DAC
5 Select/
Control
6 Logic
14-Bit
Data
and
Control
Register
10
10-Bit
10
DAC
Latch
2
2-Bit
Control
2
Data
Latch
Power Down/
Speed Control
DAC B
13 OUTB
REFINCD
9
AGND
8
DGND
DAC C
12 OUTC
DAC D
3
2
LDAC
PD
11 OUTD
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 TLV5604ID
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B DECEMBER 1997 REVISED JULY 2002
Terminal Functions
TERMINAL
NAME
NO.
AGND
9
AVDD
16
CS
6
DGND
8
DIN
4
DVDD
1
FS
7
PD
2
LDAC
3
REFINAB
15
REFINCD
10
SCLK
5
OUTA
14
OUTB
13
OUTC
12
OUTD
11
I/O
DESCRIPTION
Analog ground
Analog supply
I Chip select. This terminal is active low.
Digital ground
I Serial data input
Digital supply
I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
to the TLV5604.
I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
I Voltage reference input for DACs A and B.
I Voltage reference input for DACs C and D.
I Serial Clock input
O DAC A output
O DAC B output
O DAC C output
O DAC D output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 V to 2.8 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V
Operating free-air temperature range, TA: TLV5604C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV5604I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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