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Parallel DAC. TLV5619-EP Datasheet

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Parallel DAC. TLV5619-EP Datasheet






TLV5619-EP DAC. Datasheet pdf. Equivalent




TLV5619-EP DAC. Datasheet pdf. Equivalent





Part

TLV5619-EP

Description

12-Bit Parallel DAC

Manufacture

Texas Instruments

Datasheet
Download TLV5619-EP Datasheet


Texas Instruments TLV5619-EP

TLV5619-EP; ą TLV5619ĆEP 2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN SGLS124A − JULY 200 2 − REVISED DECEMBER 2003 D Controll ed Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temper ature Performance of −40°C to 125°C D Enhanced Diminishing Manufacturing S ources (DMS) Support D Enhanced Product Change Notification D Qualificat.


Texas Instruments TLV5619-EP

ion Pedigree† D Single Supply 2.7-V to 5.5-V Operation D ±0.4 LSB Differenti al Nonlinearity (DNL), ±1.5 LSB Integr al Nonlinearity (INL) D 12-Bit Parallel Interface D Compatible With TMS320 DSP D Internal Power On Reset D Settling T ime 1 µs Typ D Low Power Consumption: − 8 mW for 5-V Supply − 4.3 mW for 3-V Supply D Reference Input Buffers D Voltage Output D Monotonic .


Texas Instruments TLV5619-EP

Over Temperature D Asynchronous Update Component qualification in accordanc e with JEDEC and industry standards to ensure reliable operation over an exten ded temperature range. This includes, b ut is not limited to, Highly Accelerate d Stress Test (HAST) or biased 85/85, t emperature cycle, autoclave or unbiased HAST, electromigration, bond intermeta llic life, and mold .



Part

TLV5619-EP

Description

12-Bit Parallel DAC

Manufacture

Texas Instruments

Datasheet
Download TLV5619-EP Datasheet




 TLV5619-EP
ą
TLV5619ĆEP
2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER
WITH POWER DOWN
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree
D Single Supply 2.7-V to 5.5-V Operation
D ±0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)
D 12-Bit Parallel Interface
D Compatible With TMS320 DSP
D Internal Power On Reset
D Settling Time 1 µs Typ
D Low Power Consumption:
− 8 mW for 5-V Supply
− 4.3 mW for 3-V Supply
D Reference Input Buffers
D Voltage Output
D Monotonic Over Temperature
D Asynchronous Update
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
applications
D Battery Powered Test Instruments
D Digital Offset and Gain Adjustment
D Battery Operated/Remote Industrial
Controls
D Machine and Motion Control Devices
D Cordless and Wireless Telephones
D Speech Synthesis
D Communication Modulators
D Arbitrary Waveform Generation
DW PACKAGE
(TOP VIEW)
D2
1
D3
2
D4
3
D5
4
D6
5
D7
6
D8
7
D9
8
D10
9
D11
10
20
D1
19
D0
18
CS
17
WE
16
LDAC
15
PD
14
GND
13
OUT
12
REFIN
11
VDD
description
The TLV5619 is a 12-bit voltage output DAC with a microprocessor and TMS320 compatible parallel interface.
The 12 data bits are double buffered so that the output can be updated asynchronously using the LDAC pin.
During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V supply. The power
consumption can be lowered to 50 nW by setting the DAC to power-down mode.
The output voltage is buffered by a ×2 gain rail-to-rail amplifier, which features a Class A output stage to improve
stability and reduce settling time.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C SOP − DW
Tape and reel TLV5619QDWREP TLV5619QEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002 − 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1





 TLV5619-EP
TLV5619ĆEP
ą
2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER
WITH POWER DOWN
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
functional block diagram
12
REFIN
D0 19
D1 20
D2 1
D3 2
D4 3
D5 4
D6 5
6
D7
D8 7
D9 8
D10 9
D11 10
18
CS
17
WE
+
_
12
12-Bit
Input
Register
Resistor
String DAC
12-Bit
12
DAC
Latch
x2
13
OUT
Select
and
Control
Logic
Power-On
Reset
15
PD
16
LDAC
TERMINAL
NAME
CS
D0 (LSB)−D11 (MSB)
GND
LDAC
OUT
PD
REFIN
VDD
WE
NO.
18
19, 20,
1 − 10
14
16
13
15
12
11
17
Terminal Functions
I/O
DESCRIPTION
I Chip select
I Parallel data input
Ground
I Load DAC
O Analog output
I When low, disables all buffer amplifier voltages to reduce supply current
I Voltage reference input
Positive power supply
I Write enable
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 TLV5619-EP
ą
TLV5619ĆEP
2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER
WITH POWER DOWN
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital input voltage range to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
Supply voltage, VDD (5-V Supply)
4.5
Supply voltage, VDD (3-V Supply)
2.7
VDD = 2.7 V
2
High-level digital input voltage, VIH
VDD = 5.5 V
2.4
Low-level digital input voltage, VIL
VDD = 2.7 V
VDD = 5.5 V
Reference voltage, Vref to REFIN terminal (5-V Supply)
0
Reference voltage, Vref to REFIN terminal (3-V Supply)
0
Load resistance, RL
2
Load capacitance, CL
Operating free-air temperature, TA
− 40
NOTES: 1. The recommended operating levels for both VIH and VIL apply to all valid values of VDD.
2. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
5
3
2.048
1.024
10
MAX
5.5
3.3
0.6
0.8
VDD −1.5
VDD −1.5
100
125
UNIT
V
V
V
V
V
V
k
pF
°C
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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