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Noninverting Buffers. HC125AG Datasheet

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Noninverting Buffers. HC125AG Datasheet






HC125AG Buffers. Datasheet pdf. Equivalent




HC125AG Buffers. Datasheet pdf. Equivalent





Part

HC125AG

Description

Quad 3-State Noninverting Buffers

Manufacture

ON Semiconductor

Datasheet
Download HC125AG Datasheet


ON Semiconductor HC125AG

HC125AG; MC74HC125A, MC74HC126A Quad 3-State Non inverting Buffers High−Performance S ilicon−Gate CMOS The MC74HC125A and M C74HC126A are identical in pinout to th e LS125 and LS126. The device inputs ar e compatible with standard CMOS outputs ; with pullup resistors, they are compa tible with LSTTL outputs. The HC125A an d HC126A noninverting buffers are desig ned to be used with 3−.


ON Semiconductor HC125AG

state memory address drivers, clock driv ers, and other bus−oriented systems. The devices have four separate output e nables that are active−low (HC125A) o r active−high (HC126A). Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS , NMOS, and TTL • Operating Voltage R ange: 2.0 to 6.0 V • Low Input Curren t: 1.0 mA • High Noise Immunity .


ON Semiconductor HC125AG

Characteristic of CMOS Devices • In Co mpliance with the JEDEC Standard No. 7 A Requirements • Chip Complexity: 72 FETs or 18 Equivalent Gates • NLV Pre fix for Automotive and Other Applicatio ns Requiring Unique Site and Control Ch ange Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and a re RoHS Compliant LOGIC DIAGR.



Part

HC125AG

Description

Quad 3-State Noninverting Buffers

Manufacture

ON Semiconductor

Datasheet
Download HC125AG Datasheet




 HC125AG
MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7 A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
HC125A
Active−Low Output Enables
HC126A
Active−High Output Enables
A1
2
3
Y1
A1
2
3
Y1
OE1
1
5
A2
OE1
1
6
5
Y2
A2
6
Y2
OE2
4
9
A3
OE2
4
8 Y3
A3
9
8
Y3
OE3
10
12
A4
13
OE4
OE3
10
11
12
Y4
A4
13
OE4
PIN 14 = VCC
PIN 7 = GND
11
Y4
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 15
http://onsemi.com
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 VCC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
MARKING DIAGRAMS
14
HC12xAG
AWLYWW
1
SOIC−14 NB
14
HC
12xA
ALYWG
G
1
TSSOP−14
x
A
L, WL
Y, YY
W, WW
G or G
= 5, 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
HC125A
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
HC126A
Inputs Output
A OE Y
HH H
LH
L
XL
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74HC125A/D





 HC125AG
MC74HC125A, MC74HC126A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
Vin DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5 V
Iin
DC Input Current, per Pin
±20
mA
Iout DC Output Current, per Pin
±35
mA
ICC DC Supply Current, VCC and GND Pins
±75
mA
PD Power Dissipation in Still Air
SOIC Package†
500
mW
TSSOP Package†
450
Tstg Storage Temperature
–65 to +150
_C
TL Lead Temperature, 1 mm from Case for 10 Seconds
_C
(SOIC or TSSOP Package)
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
Vin, Vout
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
2.0
6.0
V
0
VCC
V
TA Operating Temperature, All Package Types
–55
+125
_C
tr, tf Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
0
VCC = 4.5 V
0
VCC = 6.0 V
0
1000
ns
500
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2





 HC125AG
MC74HC125A, MC74HC126A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
VCC
Test Conditions
V
VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V
2.0
|Iout| v 20 mA
3.0
4.5
6.0
VIL Maximum Low−Level Input Voltage Vout = 0.1 V
2.0
|Iout| v 20 mA
3.0
4.5
6.0
VOH Minimum High−Level Output
Vin = VIH
2.0
Voltage
|Iout| v 20 mA
4.5
6.0
VOL Maximum Low−Level Output
Voltage
Vin = VIH
Vin = VIL
|Iout| v 20 mA
|Iout| v 3.6 mA 3.0
|Iout| v 6.0 mA 4.5
|Iout| v 7.8 mA 6.0
2.0
4.5
6.0
Vin = VIL
|Iout| v 3.6 mA 3.0
|Iout| v 6.0 mA 4.5
|Iout| v 7.8 mA 6.0
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
IOZ Maximum Three−State Leakage
Current
Output in High−Impedance State 6.0
Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Current Vin = VCC or GND
6.0
(per Package)
Iout = 0 mA
Guaranteed Limit
–55 to
25_C
v 85_C v 125_C Unit
1.5
1.5
1.5
V
2.1
2.1
2.1
3.15
3.15
3.15
4.2
4.2
4.2
0.5
0.5
0.5
V
0.9
0.9
0.9
1.35
1.35
1.35
1.8
1.8
1.8
1.9
1.9
1.9
V
4.4
4.4
4.4
5.9
5.9
5.9
2.48
2.34
2.2
3.98
3.84
3.7
5.48
5.34
5.2
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.33
0.4
0.26
0.33
0.4
0.26
0.33
0.4
±0.1
±1.0
±1.0
mA
±0.5
±5.0
±10
mA
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
Symbol
Parameter
V
tPLH, Maximum Propagation Delay, Input A to Output Y
2.0
tPHL
(Figures 1 and 3)
3.0
4.5
6.0
tPLZ, Maximum Propagation Delay, Output Enable to Y
2.0
tPHZ
(Figures 2 and 4)
3.0
4.5
6.0
tPZL, Maximum Propagation Delay, Output Enable to Y
2.0
tPZH
(Figures 2 and 4)
3.0
4.5
6.0
tTLH, Maximum Output Transition Time, Any Output
2.0
tTHL
(Figures 1 and 3)
3.0
4.5
6.0
Cin Maximum Input Capacitance
Cout Maximum 3−State Output Capacitance (Output in High−Impedance State)
Guaranteed Limit
–55 to
25_C
90
36
18
15
v 85_C v 125_C Unit
115
135
ns
45
60
23
27
20
23
120
150
180
ns
45
60
80
24
30
36
20
26
31
90
115
135
ns
36
45
60
18
23
27
15
20
23
60
75
90
ns
22
28
34
12
15
18
10
13
15
10
10
10
pF
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Buffer)*
30
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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3



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