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Line Interface. DS21Q348 Datasheet

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Line Interface. DS21Q348 Datasheet






DS21Q348 Interface. Datasheet pdf. Equivalent




DS21Q348 Interface. Datasheet pdf. Equivalent





Part

DS21Q348

Description

3.3V E1/T1/J1 Line Interface



Feature


www.maxim-ic.com FEATURES Complete E1, T 1, or J1 Line Interface Unit (LIU) Supp orts Both Long-Haul And Short-Haul Trun ks Internal Software-Selectable Receive -Side Termination for 75Ω/100Ω/120 3.3V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.544MHz f or T1 Generates the Appr.
Manufacture

Maxim Integrated

Datasheet
Download DS21Q348 Datasheet


Maxim Integrated DS21Q348

DS21Q348; opriate Line Build-Outs, with and withou t Return loss, for E1 and DSX-1 and CSU Line Build-Outs for T1 AMI, HDB3, and B8ZS, Encoding/Decoding 16.384MHz, 8.19 2MHz, 4.096MHz, or 2.048MHz Clock Outpu t Synthesized to Recovered Clock Progra mmable Monitor Mode for Receiver Loopba cks and PRBS Pattern Generation/ Detect ion with Output for Received Errors Gen erates/Detects In-.


Maxim Integrated DS21Q348

Band Loop Codes, 1 to 16 Bits Including CSU Loop Codes 8-Bit Parallel or Serial Interface with Optional Hardware Mode Muxed and Nonmuxed Parallel Bus Support s Intel or Motorola Detects/Generates B lue (AIS) Alarms NRZ/Bipolar Interface for Tx/Rx Data I/O Transmit Open-Circui t Detection Receive Carrier Loss (RCL) Indication (G.775) High-Impedance State for TTIP and TRIN.


Maxim Integrated DS21Q348

G 50mA (RMS) Current Limiter DS21348/DS 21Q348 3.3V E1/T1/J1 Line Interface PI N CONFIGURATIONS 1 1 1 PRELMINARY TOP VIEW 44 1 DS21348 44 TQFP DS21Q348 49 CSBGA (7mm x 7mm) See Section 8 fo r 144-pin CSBGA pinout. ORDERING INFOR MATION PART DS21348TN CHANNEL TEMP R ANGE Single -40°C to +85°C DS21348T N+ Single -40°C to +85°C DS21348T S ingle 0°C to +70°C D.

Part

DS21Q348

Description

3.3V E1/T1/J1 Line Interface



Feature


www.maxim-ic.com FEATURES Complete E1, T 1, or J1 Line Interface Unit (LIU) Supp orts Both Long-Haul And Short-Haul Trun ks Internal Software-Selectable Receive -Side Termination for 75Ω/100Ω/120 3.3V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.544MHz f or T1 Generates the Appr.
Manufacture

Maxim Integrated

Datasheet
Download DS21Q348 Datasheet




 DS21Q348
www.maxim-ic.com
FEATURES
Complete E1, T1, or J1 Line Interface Unit
(LIU)
Supports Both Long-Haul And Short-Haul
Trunks
Internal Software-Selectable Receive-Side
Termination for 75/100/120
3.3V Power Supply
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1
Generates the Appropriate Line Build-Outs,
with and without Return loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1
AMI, HDB3, and B8ZS, Encoding/Decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock
Programmable Monitor Mode for Receiver
Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
Generates/Detects In-Band Loop Codes,
1 to 16 Bits Including CSU Loop Codes
8-Bit Parallel or Serial Interface with
Optional Hardware Mode
Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
Detects/Generates Blue (AIS) Alarms
NRZ/Bipolar Interface for Tx/Rx Data I/O
Transmit Open-Circuit Detection
Receive Carrier Loss (RCL) Indication
(G.775)
High-Impedance State for TTIP and TRING
50mA (RMS) Current Limiter
DS21348/DS21Q348
3.3V E1/T1/J1 Line Interface
PIN CONFIGURATIONS
1 1 1 PRELMINARY
TOP VIEW
44
1
DS21348
44 TQFP
DS21Q348
49 CSBGA
(7mm x 7mm)
See Section 8 for 144-pin CSBGA pinout.
ORDERING INFORMATION
PART
DS21348TN
CHANNEL
TEMP
RANGE
Single -40°C to +85°C
DS21348TN+ Single -40°C to +85°C
DS21348T
Single
0°C to +70°C
DS21348T+
Single
0°C to +70°C
DS21348GN Single -40°C to +85°C
DS21348GN+
Single -40°C to +85°C
DS21348G
Single
0°C to +70°C
DS21348G+
Single
0°C to +70°C
DS21Q348N
Four
-40°C to +85°C
DS21Q348
Four
0°C to +70°C
+ Denotes lead-free/RoHS-compliant package.
PIN-PACKAGE
44 TQFP
44 TQFP
44 TQFP
44 TQFP
49 CSBGA
49 CSBGA
49 CSBGA
49 CSBGA
144 CSBGA
144 CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 011206




 DS21Q348
DS21348/DS21Q348
DETAILED DESCRIPTION
The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75or 120applications and DSX-1 line build-outs or CSU line build-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8).
The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-
bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an
8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all
of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,
JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
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 DS21Q348
DS21348/DS21Q348
TABLE OF CONTENTS
1. INTRODUCTION.................................................................................................................. 6
1.1 DOCUMENT REVISION HISTORY...............................................................................................6
2. PIN DESCRIPTION............................................................................................................ 10
2.1 PIN DESCRIPTIONS........................................................................................................................14
3. HARDWARE MODE .......................................................................................................... 25
3.1 REGISTER MAP .............................................................................................................................25
3.2 PARALLEL PORT OPERATION .........................................................................................................26
3.3 SERIAL PORT OPERATION..............................................................................................................26
4. CONTROL REGISTERS .................................................................................................... 29
4.1 DEVICE POWER-UP AND RESET .....................................................................................................32
5. STATUS REGISTERS ....................................................................................................... 36
6. DIAGNOSTICS .................................................................................................................. 41
6.1 IN-BAND LOOP CODE GENERATION AND DETECTION ......................................................................41
6.2 LOOPBACKS ..................................................................................................................................46
6.2.1 Remote Loopback (RLB) ..................................................................................................................... 46
6.2.2 Local Loopback (LLB) .......................................................................................................................... 46
6.2.3 Analog Loopback (ALB) ....................................................................................................................... 46
6.2.4 Dual Loopback (DLB)........................................................................................................................... 46
6.3 PRBS GENERATION AND DETECTION ............................................................................................47
6.4 ERROR COUNTER..........................................................................................................................47
6.4.1 Error Counter Update........................................................................................................................... 48
6.5 ERROR INSERTION ........................................................................................................................48
7. ANALOG INTERFACE ...................................................................................................... 49
7.1 RECEIVER .....................................................................................................................................49
7.2 TRANSMITTER ...............................................................................................................................50
7.3 JITTER ATTENUATOR .....................................................................................................................50
7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................51
8. DS21Q348 QUAD LIU ....................................................................................................... 58
9. DC CHARACTERISTICS ................................................................................................... 62
10. THERMAL CHARACTERISTICS....................................................................................... 63
11. AC CHARACTERISTICS ................................................................................................... 64
12. PACKAGE INFORMATION ............................................................................................... 73
12.1 44-PIN TQFP (56-G4012-001) .....................................................................................................73
12.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001) ...........................................................................74
12.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001) .....................................................................75
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