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Clock Buffer. LMH2180 Datasheet

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Clock Buffer. LMH2180 Datasheet






LMH2180 Buffer. Datasheet pdf. Equivalent




LMH2180 Buffer. Datasheet pdf. Equivalent





Part

LMH2180

Description

Dual Clock Buffer



Feature


LMH2180 www.ti.com SNAS419D – JANUAR Y 2008 – REVISED MARCH 2013 LMH2180 75 MHz Dual Clock Buffer Check for Samp les: LMH2180 FEATURES 1 •2 (Typical Values are: VSUPPLY = 2.7V and CL = 10 pF, unless Otherwise Specified.) • Sm all Signal Bandwidth 78 MHz • Supply Voltage Range 2.4V to 5V • Phase Nois e (VIN = 1 VPP, fC = 38.4 MHz, Δf = 1 kHz) −123 dBc/Hz • Slew Rate 10.
Manufacture

Texas Instruments

Datasheet
Download LMH2180 Datasheet


Texas Instruments LMH2180

LMH2180; 6 V/μs • Total Supply Current 2.3 mA • Shutdown Current 30 µA • Rail-to -Rail Input and Output • Individual B uffer Enable Pins • Rapid Ton Technol ogy • Crosstalk Rejection Circuitry Packages: – 8-Pin WSON, Solder Bum p and no Pullback – 8-Bump DSBGA • Temperature Range −40°C to 85°C APP LICATIONS • 3G Mobile Applications WLAN–WiMAX Modules • TD_SCDMA Multi-Mode MP3 a.


Texas Instruments LMH2180

nd Camera • GSM Modules • Oscillator Modules DESCRIPTION The LMH2180 is a high speed dual clock buffer designed f or portable communications and applicat ions requiring multiple accurate multi- clock systems. The LMH2180 integrates t wo 75 MHz low noise buffers with indepe ndent shutdown pins into a small packag e. The LMH2180 ensures superb system op eration between the ba.


Texas Instruments LMH2180

seband and the oscillator signal path by eliminating crosstalk between the mult iple clock signals. Unique technology a nd design provides the LMH2180 with the ability to accurately drive both large capacitive and resistive loads. Low su pply current combined with shutdown pin s for each channel means the LMH2180 is ideal for battery powered applications . This part does n.

Part

LMH2180

Description

Dual Clock Buffer



Feature


LMH2180 www.ti.com SNAS419D – JANUAR Y 2008 – REVISED MARCH 2013 LMH2180 75 MHz Dual Clock Buffer Check for Samp les: LMH2180 FEATURES 1 •2 (Typical Values are: VSUPPLY = 2.7V and CL = 10 pF, unless Otherwise Specified.) • Sm all Signal Bandwidth 78 MHz • Supply Voltage Range 2.4V to 5V • Phase Nois e (VIN = 1 VPP, fC = 38.4 MHz, Δf = 1 kHz) −123 dBc/Hz • Slew Rate 10.
Manufacture

Texas Instruments

Datasheet
Download LMH2180 Datasheet




 LMH2180
LMH2180
www.ti.com
SNAS419D – JANUARY 2008 – REVISED MARCH 2013
LMH2180 75 MHz Dual Clock Buffer
Check for Samples: LMH2180
FEATURES
1
2 (Typical Values are: VSUPPLY = 2.7V and CL = 10
pF, unless Otherwise Specified.)
• Small Signal Bandwidth 78 MHz
• Supply Voltage Range 2.4V to 5V
• Phase Noise (VIN = 1 VPP, fC = 38.4 MHz, Δf = 1
kHz) 123 dBc/Hz
• Slew Rate 106 V/μs
• Total Supply Current 2.3 mA
• Shutdown Current 30 µA
• Rail-to-Rail Input and Output
• Individual Buffer Enable Pins
• Rapid Ton Technology
• Crosstalk Rejection Circuitry
• Packages:
– 8-Pin WSON, Solder Bump and no Pullback
– 8-Bump DSBGA
• Temperature Range 40°C to 85°C
APPLICATIONS
• 3G Mobile Applications
• WLAN–WiMAX Modules
• TD_SCDMA Multi-Mode MP3 and Camera
• GSM Modules
• Oscillator Modules
DESCRIPTION
The LMH2180 is a high speed dual clock buffer
designed for portable communications and
applications requiring multiple accurate multi-clock
systems. The LMH2180 integrates two 75 MHz low
noise buffers with independent shutdown pins into a
small package. The LMH2180 ensures superb
system operation between the baseband and the
oscillator signal path by eliminating crosstalk between
the multiple clock signals.
Unique technology and design provides the LMH2180
with the ability to accurately drive both large
capacitive and resistive loads. Low supply current
combined with shutdown pins for each channel
means the LMH2180 is ideal for battery powered
applications. This part does not use an internal
ground reference, thus providing additional system
flexibility.
The flexible buffers provide system designers the
capacity to manage complex clock signals in the
latest wireless applications. Each buffer delivers 106
V/μs internal slew rate with independent shutdown
and duty cycle precision. Each input is internally
biased to 1V, removing the need for external
resistors. Both channels have rail-to-rail inputs and
outputs, a gain of one, and are AC coupled with the
use of one capacitor.
Replacing a discrete buffer solution with the
LMH2180 provides many benefits: simplified board
layout, minimized parasitic components, simplified
BOM, design durability across multiple applications,
simplification of clock paths, and the ability to reduce
the number of clock signal generators in the system.
The LMH2180 is produced in the tiny packages
minimizing the required PCB space.
TYPICAL APPLICATION
Enable 1
VCTCXO
10 nF
VCC
EN1 8
1
IN1 2
1
7 OUT1
LMH2180
Rload
LOAD1
Cload
Enable 2
IN2 3
2
EN2 4
5
6 OUT2
GND
Rload
LOAD2
Cload
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated




 LMH2180
LMH2180
SNAS419D – JANUARY 2008 – REVISED MARCH 2013
CONNECTION DIAGRAMS
Top View
VDD 1
IN 1 2
IN 2 3
DEVICE
CODE
8 ENABLE 1
7 OUT 1
6 OUT 2
www.ti.com
VDD A3
Top View
EN1
B3
C3 OUT1
IN1 A2
C2 OUT2
ENABLE 2 4
5 VSS
Figure 1. 8-Pin WSON Package
See Package Number NGW0008A or NGQ0008A
IN2 A1
B1
C1
VSS
EN2
Figure 2. 8-Bump DSBGA Package
See Package Number YFQ0008AAA
Pin No.
WSON
1
2
3
4
5
6
7
8
Pin No.
DSBGA
A3
A2
A1
B1
C1
C2
C3
B3
Pin Name
VDD
IN 1
IN 2
ENABLE 2
VSS
OUT 2
OUT 1
ENABLE 1
PIN DESCRIPTIONS
Voltage supply connection
Input 1
Input 2
Enable buffer 2
Ground connection
Output 2
Output 1
Enable buffer 1
Description
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)
Supply Voltages (V+ – V)
ESD Tolerance
Human Body (3)
Machine Model (4)
Charged Device Model
Storage Temperature Range
Junction Temperature (5)
Soldering Information
Infrared or Convection (35 sec.)
5.5V
2000V
200V
1000V
65°C to 150°C
150°C
235°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, applicable std. JESD22–A114C.
(4) Machine model, applicable std. JESD22–A115–A.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA , and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower.
2
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Copyright © 2008–2013, Texas Instruments Incorporated




 LMH2180
LMH2180
www.ti.com
SNAS419D – JANUARY 2008 – REVISED MARCH 2013
OPERATING RATINGS (1)
Supply Voltage (V+ – V)
Temperature Range (2)(3)
Package Thermal Resistance (2)(3)
2.4V to 5.0V
40°C to 85°C
8-Pin WSON (θJA)
8-Bump DSBGA (θJA)
217°C/W
90°C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise
modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by
production tests. Individual parts may vary.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA , and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower.
2.7V ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10
pF, RL = 30 k, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of
operating condition.(1)
Parameter
Test Conditions
Min (2)
Typ (3) Max (2)
Units
Frequency Domain Response
SSBW
LSBW
GFN
Small Signal Bandwidth
Large Signal Bandwidth
Gain Flatness < 0.1 dB
VIN = 100 mVPP; 3 dB
VIN = 1.0 VPP; 3 dB
f > 100 kHz
78
MHz
60
MHz
4.9
MHz
Distortion and Noise Performance
φn
Phase Noise
VIN = 1 VPP, fC = 38.4 MHz, Δf = 1 kHz
VIN = 1 VPP, fC = 38.4 MHz, Δf = 10
kHz
123
132
dBc/Hz
dBc/Hz
en
ISOLATION
CT
Input-Referred Voltage Noise
Output to Input
Crosstalk Rejection
Time Domain Response
f = 1 MHz, RSOURCE = 50
f = 1 MHz, RSOURCE = 50
f = 38.4 MHz, VIN = 1 VPP
13
nV/Hz
84
dB
41
dB
tr
Rise Time
tf
Fall Time
ts
Settling Time to 0.1%
OS
Overshoot
SR
Slew Rate (4)
Static DC Performance
0.1 VPP Step (10-90%)
1 VPP Step
0.1 VPP Step
VIN = 2 VPP
6
ns
5
ns
120
ns
37
%
106
V/µs
IS
Supply Current
Enable1,2 = VDD ; No Load
2.3
2.7
2.9
mA
Enable1 = VDD , Enable2 = VSS , No
Load
1.3
1.5
1.6
mA
Enable1,2 = VSS ; No Load
30
41
46
μA
PSRR
Power Supply Rejection Ratio
DC (3.0V to 5.0V)
65
64
68
dB
(1) The Electrical Characteristics tables show performance under the specified Recommended Operating Conditions except as otherwise
modified by the Electrical Characteristics Conditions and/or Notes. Typical values represent typical performance as measured by
production tests. Individual parts may vary.
(2) Datasheet min/max limits are specified by test or statistical analysis.
(3) Typical values represent the most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization.
(4) Slew rate is the average of the rising and falling slew rates.
Copyright © 2008–2013, Texas Instruments Incorporated
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3
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