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Tree Driver. LMH2191 Datasheet

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Tree Driver. LMH2191 Datasheet






LMH2191 Driver. Datasheet pdf. Equivalent




LMH2191 Driver. Datasheet pdf. Equivalent





Part

LMH2191

Description

Dual Channel Clock Tree Driver



Feature


LMH2191 www.ti.com SNAS485D – JULY 2 010 – REVISED MAY 2013 LMH2191 Dual Channel 52 MHz Clock Tree Driver Check for Samples: LMH2191 FEATURES 1 •2 O ne Input Clock, Two Output Clocks • 1 .8V Square Wave Clock Outputs • Inver ted Clock Outputs • Independent Clock Requests • High Isolation of Supply Noise to Clock Input • High Output-to -Output Isolation • Integrated 1.8.
Manufacture

Texas Instruments

Datasheet
Download LMH2191 Datasheet


Texas Instruments LMH2191

LMH2191; V Low-Dropout Regulator – Low Output-N oise Voltage – 10 mA Load Current • EMI Filtering • Ultra Low Standby Cu rrent • VBAT Range = 2.5V to 5.5V • 8-Bump DSBGA Package APPLICATIONS • Mobile Handsets • Portable Equipment DESCRIPTION The LMH2191 is a dual-chan nel clock tree driver that supplies a d igital system clock to peripherals in m obile handsets or other applicatio.


Texas Instruments LMH2191

ns. It provides a solution to clocking i ssues such as limited drive capability for fanout or longer traces. It also pr ovides protection of the master clock f rom varying loads and frequency pulling effects, isolation from noisy modules, and crosstalk isolation. It has very l ow phase noise which enables it to driv e sensitive modules such as Wireless LA N and Bluetooth. T.


Texas Instruments LMH2191

he LMH2191 can be clocked up to 52 MHz a nd has an independent clock request pin for each clock output which allows the peripheral to control the clock. It fe atures an integrated LDO which provides an ultra low-noise voltage supply with 10 mA external load current which can be used to supply the TCXO or other clo ck source. The LMH2191 dual clock distr ibutor is offered .

Part

LMH2191

Description

Dual Channel Clock Tree Driver



Feature


LMH2191 www.ti.com SNAS485D – JULY 2 010 – REVISED MAY 2013 LMH2191 Dual Channel 52 MHz Clock Tree Driver Check for Samples: LMH2191 FEATURES 1 •2 O ne Input Clock, Two Output Clocks • 1 .8V Square Wave Clock Outputs • Inver ted Clock Outputs • Independent Clock Requests • High Isolation of Supply Noise to Clock Input • High Output-to -Output Isolation • Integrated 1.8.
Manufacture

Texas Instruments

Datasheet
Download LMH2191 Datasheet




 LMH2191
LMH2191
www.ti.com
SNAS485D – JULY 2010 – REVISED MAY 2013
LMH2191 Dual Channel 52 MHz Clock Tree Driver
Check for Samples: LMH2191
FEATURES
1
2 One Input Clock, Two Output Clocks
• 1.8V Square Wave Clock Outputs
• Inverted Clock Outputs
• Independent Clock Requests
• High Isolation of Supply Noise to Clock Input
• High Output-to-Output Isolation
• Integrated 1.8V Low-Dropout Regulator
– Low Output-Noise Voltage
– 10 mA Load Current
• EMI Filtering
• Ultra Low Standby Current
• VBAT Range = 2.5V to 5.5V
• 8-Bump DSBGA Package
APPLICATIONS
• Mobile Handsets
• Portable Equipment
DESCRIPTION
The LMH2191 is a dual-channel clock tree driver that
supplies a digital system clock to peripherals in
mobile handsets or other applications. It provides a
solution to clocking issues such as limited drive
capability for fanout or longer traces. It also provides
protection of the master clock from varying loads and
frequency pulling effects, isolation from noisy
modules, and crosstalk isolation. It has very low
phase noise which enables it to drive sensitive
modules such as Wireless LAN and Bluetooth.
The LMH2191 can be clocked up to 52 MHz and has
an independent clock request pin for each clock
output which allows the peripheral to control the
clock. It features an integrated LDO which provides
an ultra low-noise voltage supply with 10 mA external
load current which can be used to supply the TCXO
or other clock source. The LMH2191 dual clock
distributor is offered in a tiny 1.61 mm x 1.063 mm 8-
bump DSBGA package. Its small size and low supply
current make it ideal for portable applications.
Typical Application
VBAT
CCLK
10 nF
VDD
Clock
Source
CBAT
1 µF
VBAT
A1
LMH2191
VOUT B1
1.8V LDO
COUT
2.2 µF
A2 CLK1
SCLK_IN C1
CSERIES
Clock
Tree
Driver
D2 CLK2
Peripheral
Peripheral
Clock
Request
D1
VSS
B2 CLK_REQ1
C2 CLK_REQ2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated




 LMH2191
LMH2191
SNAS485D – JULY 2010 – REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage
VBAT - VSS
LVCMOS port IO voltage
ESD Tolerance(3)
Human Body Model
Machine Model
Charge Device Model
Output Short Circuit Duration(4)
LDO
Clock Output
For Soldering Information see http://www.ti.com/lit/SNOA549
Storage Temperature Range
Junction Temperature(5)
-0.3V to 6V
-0.3V to (VOUT + 0.3V)
2000V
200V
1000V
infinite
infinite
65°C to 150°C
150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For specifications and the test conditions, see
the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, applicable std. MIL-STD-883, Method 3015.7. Machine model, applicable std. JESD22–A115–A (ESD MM std of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C. (ESD FICDM std. of JEDEC)
(4) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 1500C.
(5) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
OPERATING RATINGS(1)
Supply Voltage (VBAT - VSS)
Input Clock, SCLK_IN
Temperature Range
Package Thermal Resistance θJA(2)
Package YFX
Frequency
Duty Cycle
2.5V to 5.5V
10 MHz to 52 MHz
45% to 55%
-40°C to +85°C
Board specification: 4LCELLPHONE
153 °C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For specifications and the test conditions, see
the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
2
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Copyright © 2010–2013, Texas Instruments Incorporated




 LMH2191
LMH2191
www.ti.com
SNAS485D – JULY 2010 – REVISED MAY 2013
3.5 V ELECTRICAL CHARACTERISTICS(1)
Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF(2), fSCLK_IN = 26 MHz,
IOUT = 1mA, Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min (3)
Typ (4)
Max (3)
Units
Supply Current(5)(6)
IDD
Supply Current
Active Mode SCLK_IN = 19.2 MHz;
both clock outputs toggling; CLOAD
CLK1/2 = 0pF; IOUT = 0mA
Active Mode SCLK_IN = 19.2 MHz;
both clock outputs toggling; CLOAD for
CLK1/2 = 33.5pF; IOUT = 0mA
Active Mode SCLK_IN = 26 MHz, both
clock outputs toggling, CLOAD for
CLK1/2 = 0pF, IOUT=0mA
Active Mode SCLK_IN = 26 MHz, both
clock outputs toggling, CLOAD for
CLK1/2 = 33.5 pF, IOUT=0mA
In shutdown. Input clock not active.
CLK_REQ1/2=Low
1.4
1.65
1.7
mA
3.7
4.45
4.50
mA
1.9
2.15
2.25
mA
5
5.80
5.95
mA
0.1
1
µA
In shutdown. Input clock toggling.
CLK_REQ1/2=Low
0.1
1
uA
CPD
Power Dissipation Capacitance
per CLK output
Clock Outputs (CLK1/2) Figure 1, Figure 2
CLOAD for CLK1,2 = 0pF, Defined with
respect to VOUT = 1.8V
20
23.0
24.0
pF
tPD_LH
Propagation Delay - Low to High 50% to 50%;
CLOAD = 33 pF; measured on CLK1
6.1
10.5
tPD_HL
Propagation Delay - High to Low 50% to 50%;
CLOAD = 33 pF; measured on CLK1
6.1
10.5
ns
tSKEW
Skew Between Outputs (Either
Edge)
CLK1 to CLK2. 50% to 50%
1.5
3.1
tRISE
tFALL
Rise Time(7)
Fall Time(7)
For CL between 33.5 pF - 50 pF, 20% to
80%; typical value based on 40 pF load
2.1
3.7
5.9
ns
For CL between 33.5 pF - 50 pF, 20% to
80%; typical value based on 40pF load
2
3.5
5
CLK_DC
JitterRMS
Output Clock Duty Cycle
Additive RMS period Jitter
For CL between 33.5 pF - 50 pF
fSCLK-IN= 26 MHz, BW = CLK1
100 Hz to 1MHz
CLK2
42
50
58
%
95
fs
110
(1) Electrical Table values apply only for factory testing (ATE) conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > TA.
(2) CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(3) Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality
control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(5) Supply current depends on switching frequency and load.
(6) Positive current is current flowing into the device.
(7) This parameter is specified by design and/or characterization and is not tested in production.
Copyright © 2010–2013, Texas Instruments Incorporated
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3
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