Quad 2-input AND gate
74ABT08
Quad 2-input AND gate
Rev. 4 — 7 October 2020
Product data sheet
1. General description
The 74ABT08 is a quad ...
Description
74ABT08
Quad 2-input AND gate
Rev. 4 — 7 October 2020
Product data sheet
1. General description
The 74ABT08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 4.5 V to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection:
HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range Name
74ABT08D
-40 °C to +85 °C SO14
74ABT08PW -40 °C to +85 °C TSSOP14
Description
plastic small outline package; 14 leads; body width 3.9 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version SOT108-1
SOT402-1
Nexperia
4. Functional diagram
1
&
3
2
1 1A 2 1B
4 2A 5 2B
9 3A 10 3B
12 4A 13 4B
1Y 3 2Y 6 3Y 8 4Y 11
mna222
Fig. 1. Logic symbol
4
&
6
5
9
&
8
10
12
&
11
13
mna223
Fig. 2. IEC logic symbol
5. Pinning information
74ABT08
Quad 2-input AND gate
A Y
B
mna221
Fig. 3. Logic diagram (one gate)
5.1. Pinning
74ABT08
1A 1 1B 2
14 VCC 13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
...
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