3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
D Inputs Are TTL-Voltage Compatible D Designed Specif...
Description
SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
SCLS266M − DECEMBER 1995 − REVISED JULY 2003
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)
SN54AHCT138 . . . J OR W PACKAGE SN74AHCT138 . . . D, DB, DGV, N, NS,
OR PW PACKAGE (TOP VIEW)
A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8
16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
SN74AHCT138 . . . RGY PACKAGE (TOP VIEW)
VCC
A
1
B2 C3 G2A 4 G2B 5 G1 6 Y7 7
8
16
15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9
SN54AHCT138 . . . FK PACKAGE (TOP VIEW)
Y0
VCC
NC
A
B
C G2A
NC G2B
G1
3 2 1 20 19
4
18 Y1
5
17 Y2
6
16 NC
7
15 Y3
8
14 Y4
9 10 11 12 13
Y7
Y6
Y5
NC
GND
Y6
GND
NC − No internal connection
description/ordering information
The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are...
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