SN54AHCT132

D Inputs Are TTL-Voltage Compatible D Operation From Very Slow Input Transitions D Temperature-Compensated Threshold Levels D High Noise Immunity D Same Pinouts as ’AHCT00 D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 SN54AHCT132 . . . J OR W PACKAGE SN74AHCT132 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y SN54AHCT132 . . . FK PACKAGE (TOP VIEW) 4B VCC NC 1A 1B description The ’AHCT132 devices are quadruple positive-NAND gates. These devices perform the Boolean function Y = A B or Y = A + B in positive logic. Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. 3 2 1 20 19 1Y 4 18 4A NC 5 17 NC 2A 6 16 4Y NC 7 15 NC 2B 8 14 3B 9 10 11 12 13 3A 3Y NC GND 2Y NC – No internal connection ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74AHCT132N SN74AHCT132N SOIC – D Tube Tape and reel SN74AHCT132D SN74AHCT132DR AHC...