Dual J-K Negative-edge-triggered Flip-Flops
HD74LS107A
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300 Rev.3.00
Jul.13.2005
Features
• Ord...
Description
HD74LS107A
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300 Rev.3.00
Jul.13.2005
Features
Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74LS107AP
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
HD74LS107AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B
FP
(FP-14DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity) —
EL (2,000 pcs/reel)
Pin Arrangement
1J 1 1Q 2 1Q 3 1K 4 2Q 5 2Q 6 GND 7
CLR J Q CK
Q
K
Q
K
Q CK CLR J
(Top view)
14 VCC 13 1CLR 12 1CK 11 2K 10 2CLR 9 2CK 8 2J
Function Table
Inputs
Outputs
Clear
Clock
J
K
Q
Q
L
X
X
X
L
H
H
↓
L
L
QO
QO
H
↓
H
L
H
L
H
↓
L
H
L
H
H
↓
H
H
Toggle
H
H
X
X
QO
QO
Notes: H; high level, L; low level, X; irrelevant
↓; transition from high to low level
Q; level of Q before the indicated steady-state input conditions were established.
Q; complement of QO or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
Rev.3.00, Jul.13.2005, page 1 of 6
HD74LS107A
Block Diagram (1/2)
Q
Q
Clear
K
J
Clock
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN
7
Power dissipation
PT
400
Storage temperature
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to net...
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