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HD74LS112P Dataheets PDF



Part Number HD74LS112P
Manufacturers Renesas
Logo Renesas
Description Dual J-K Negative-edge-triggered Flip-Flops
Datasheet HD74LS112P DatasheetHD74LS112P Datasheet (PDF)

HD74LS112 Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) REJ03D0426–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS112P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS112FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) HD74LS112RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP Note: Please consult the sales office for the above package availability. Taping Abbreviation.

  HD74LS112P   HD74LS112P


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HD74LS112 Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) REJ03D0426–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS112P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS112FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) HD74LS112RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) Pin Arrangement 1CK 1 1K 2 1J 3 1PR 4 1Q 5 1Q 6 2Q 7 GND 8 J CK K PR CLR Q Q K CK J CLR PR Q Q 16 VCC 15 1CLR 14 2CLR 13 2CK 12 2K 11 2J 10 2PR 9 2Q (Top view) Rev.3.00, Jul.13.2005, page 1 of 8 HD74LS112 Function Table Inputs Outputs Preset Clear Clock J K Q Q L H X X X H L H L X X X L H L L X X X H* H* H H ↓ L L QO QO H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X QO QO Notes: H; high level, L; low level, X; irrelevant ↓; transition from high to low level Q; level of Q before the indicated steady-state input conditions were established. Q; complement of QO or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. *; This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. Block Diagram (1/2) Q Preset K Clock Q Clear J Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V Power dissipation Storage temperature PT Tstg 400 mW –65 to +150 °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.3.00, Jul.13.2005, page 2 of 8 HD74LS112 Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Clock High Pulse width Clear Preset Low Setup time “H” Data “L” Data Hold time Symbol VCC IOH IOL Topr fclock tw tsu th Min 4.75 — — –20 0 20 25 20↓ 20↓ 0↓ Typ Max Unit 5.00 5.25 V — –400 µA — 8 mA 25 75 °C — 30 MHz — — ns — — ns ns — — ns — — ns Electrical Characteristics (Ta = –20 to +75 °C) Item Symbol min. typ.* max. Unit Condition Input voltage Output voltage J, K VIH 2.0 — — V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V, — — 0.4 IOL = 4 mA VIL = 0.8 V — — 20 Clear — — 60 Preset IIH — — 60 µA VCC = 5.25 V, VI = 2.7 V Clock — — 80 J, K — — –0.4 Input Clear — — –0.8 current Preset IIL** — — –0.8 mA VCC = 5.25 V, VI = 0.4 V Clock — — –0.8 J, K — — 0.1 Clear — — 0.3 Preset II — — 0.3 mA VCC = 5.25 V, VI = 7 V Clock — — 0.4 Short-circuit output current IOS –20 — –100 mA VCC = 5.25 V Supply current*** ICC — 4 8 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** IIL should not be measured when preset and clear inputs are low at same time. *** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the tires of measurement, the clock input is grounded. Switching Characteristics Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL Inputs Clear Preset Clock (VCC = 5 V, Ta = 25°C) Outputs min. typ. max. Unit Condition 30 45 — MHz Q, Q — 11 20 ns CL = 15 pF, RL = 2 kΩ — 15 30 ns Rev.3.00, Jul.13.2005, page 3 of 8 HD74LS112 Timing Definition tw Clock J, K 1.3 V tsu 1.3 V th 1.3 V "H" Data 1.3 V 3V 1.3 V 0V tsu th 3V "L" Data 1.3 V 0V Testing Method Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q) VCC Output Q Input 4.5V P.G. Zout=50Ω PR J CK K CLR Q Output Q Q Load circuit 1 RL CL Same as Load Circuit 1. Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Rev.3.00, Jul.13.2005, page 4 of 8 HD74LS112 2. tPHL, tPLH, (Clear, Preset→Q, Q) Input P.G. Zout=50Ω 4.5V Input P.G. Zout=50Ω VCC Output Q PR J Q CK K CLR Output Q Q Load circuit 1 RL CL Same as Load Circuit 1. Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Waveforms 1 Clock Q 10% tTLH tTHL 90% 90% tw(L) 1.3 V 1.3 V 10% tw(H) tPLH 1.3 V 1.3 V tPHL 1.3 V tPHL 1.3 V tPLH 3V 0V VOH VOL Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and: for fmax, tTHL tTHL ≤ 2.5 ns. Rev.3.00, Jul.13.2005, page 5 of 8 .


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