Document
Preliminary Datasheet
HD74LS74A
Dual D-type Positive Edge-triggered Flip-Flops (with Preset and Clear)
R04DS0012EJ0400 (Previous: REJ03D0415-0300)
Rev.4.00 Dec 21, 2011
Features
Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74LS74AP
DILP-14 pin
PRDP0014AB-B (DP-14AV)
P
PRSP0014DF-B
HD74LS74AFPEL SOP-14 pin (JEITA)
(FP-14DAV)
FP
HD74LS74ARPEL SOP-14 pin (JEDEC) PRSP0014DE-A
RP
(FP-14DNV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity) —
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Pin Arrangement
1CLR 1 1D 2
1CK 3 1PR 4
1Q 5 1Q 6 GND 7
CK D PR CLR
QQ
D CK CLR PR
QQ
(Top view)
14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q
Function Table
Input
Preset
Clear
Clock
D
Output
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
H; high level, L; low level, X; irrelevant, ; transition from low to high level,
Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
*;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level.
R04DS0012EJ0400 Rev.4.00 Dec 21, 2011
Page 1 of 7
HD74LS74A
Preliminary
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage Input voltage Power dissipation Storage temperature
VCC VIN PT Tstg
7
V
7
V
400
mW
–65 to +150
C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Supply voltage
VCC
Output current
IOH
IOL
Operating temperature
Topr
Clock frequency
fclock
Pulse width
Clock High
tw
Clear Preset
tw
Setup time
“H” Data
tsu
“L” Data
tsu
Hold time
th
Note: ; The arrow indicates the rising edge.
Min 4.75 — — –20
0 25 25 20 20 5
Typ 5.00 — — 25 — — — — — —
Max 5.25 –400
8 75 25 — — — — —
Unit V A mA C
MHz
ns
ns
ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol
min.
typ.* max.
Unit
Condition
Input voltage Output voltage
D
VIH
2.0
—
—
V
VIL
—
—
0.8
V
VOH
2.7
—
—
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 A
VOL
—
—
0.5
V
IOL = 8 mA VCC = 4.75 V, VIL = 0.8 V,
—
—
0.4
IOL = 4 mA VIH = 2 V
—
—
20
Clear
—
—
40
Preset
IIH
—
—
40
A VCC = 5.25 V, VI = 2.7 V
Clock
—
—
20
D
—
—
–0.4
Input current
Clear Preset
—
—
–0.8
IIL
—
—
–0.8
mA VCC = 5.25 V, VI = 0.4 V
Clock
—
—
–0.4
D
—
—
0.1
Clear
—
—
0.2
Preset
II
—
—
0.2
mA VCC = 5.25 V, VI = 7 V
Clock
—
—
0.1
Short-circuit output current
IOS
–20
—
–100
mA VCC = 5.25 V
Supply current
ICC**
—
4
8
mA VCC = 5.25 V
Input clamp voltage
VIR
—
—
–1.5
V
VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** With all output open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the
clock input is grounded.
R04DS0012EJ0400 Rev.4.00 Dec 21, 2011
Page 2 of 7
HD74LS74A
Preliminary
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol
Inputs
Outputs min. typ. max. Unit
Condition
Maximum clock frequency fmax
Propagation delay time
tPLH
Clear, Clock Q, Q
tPHL
or Preset
25 — —
33 13 25
MHz
25
ns
CL = 15 pF, RL = 2 k
40
ns
Timing Definition
tw
Clock Data
1.3 V tsu
1.3 V th
1.3 V
tsu
th
1.3 V
"H" Data
1.3 V
"L" Data
3V
0V
3V 1.3 V
0V
R04DS0012EJ0400 Rev.4.00 Dec 21, 2011
Page 3 of 7
HD74LS74A
Testing Method
Test Circuit 1. max, tPLH, tPHL (ClockQ, Q)
Input
P.G. Zout = 50Ω
Input
P.G. Zout = 50Ω
Preliminary
4.5V VCC Output Q
PR
D
Q
CK CLR
Output Q Q
Load circuit 1 RL CL Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
2. tPHL, tPLH (Clear or Preset Q, Q)
Input P.G. Zout = 50Ω
Input P.G. Zout = 50Ω
VCC Output Q
PR
D
Q
CK CLR
Output Q Q
Load circuit 1 RL CL Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
R04DS0012EJ0400 Rev.4.00 Dec 21, 2011
Page 4 of 7
HD74LS74A Waveforms 1
Clock
tTLH
tTHL
10%
90% 90% 1.3 V 1.3 V
tw(H)
tw(L) 10%
1.3 V
Preliminary
3V 0V 3V
D tPLH
1.3 V Q
tPHL
tPHL 1.3 V
tPLH
0V VOH VOL
Note:
Q 1.3 V
VOH 1.3 V
VOL
Clock input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL 2.5 ns
Waveforms 2
Clear Preset
Q
tTHL
tTLH
90% 1.3V 10%
tw (clear) ≥ 25ns
90% 1.3V 10%
tPHL
1.3V tPLH
3V
tTHL
tTLH
90% 1.3V 10%
tw (preset) ≥ 25ns tPLH
90% 1.3V 10.