HD74LS75P

HD74LS75 Quadruple Bistable Latches REJ03D0416-0300 Rev.3.00 May 10, 2006 The HD74LS75 is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. This device features complementary Q and Q outputs from a 4-bit latch. Features Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviation HD74LS75P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS75FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) Pin Arrangement 1Q 1 1D 2 2D 3 Enable 3-4 4 VCC 5 3D 6 4D 7 4Q 8 Q Q GD GD Q Q Q Q GD GD Q Q 16 1Q 15 2Q 14 2Q 13 Enable 1-2 12 GND 11 3Q 10 3Q 9 4Q (Top view) Rev.3.00, May 10, 2006, page 1 of 5 HD74LS75 Function Table Inputs Outputs D G Q Q L H L H H H H L X L Q0 Q0 H; high level, L; low level, X; irrelevant Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q0 before the indicate...