Differential Translator/Repeater
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SN65LVDS100,...
Description
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Reference Design
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101
SLLS516E – AUGUST 2002 – REVISED JULY 2015
SN65LVDx10x Differential Translator/Repeater
1 Features
1 Designed for Signaling Rates ≥ 2 Gbps Total Jitter < 65 ps Low-Power Alternative for the MC100EP16 Low 100-ps (Maximum) Part-to-Part Skew 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels 3.3-V Supply Operation LVDT Integrates 110-Ω Terminating Resistor Offered in SOIC and MSOP
2 Applications
Wireless Infrastructure Telecom Infrastructure Printers
3 Description
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65LVDS100
SOIC (8) VSSOP (8)
4.90 mm × 3.91 mm 3.00 mm × 3.00 mm
SN65LVDT100
SOIC (8) VSSOP (8)
4.90 mm × 3.91 mm 3.00 mm × 3.00 mm
SN65LVDS101
SOIC (8) VSSOP (8)
4.90 mm × 3.91 mm 3.00 mm × 3.00 mm
SN65LVDT101
SO...
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