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NIS2161 Dataheets PDF



Part Number NIS2161
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description ESD Protection
Datasheet NIS2161 DatasheetNIS2161 Datasheet (PDF)

NIV2161, NIS2161 ESD Protection with Automotive Short-toBattery & Ground Protection Low Capacitance ESD Protection w/ short− to−battery and short−to−ground Protection for Automotive High Speed Data Lines The NIS/NIV2161 is designed to protect high speed data lines from ESD as well as short to vehicle battery situations. The ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines while the low RDS(on) FET limits.

  NIS2161   NIS2161


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NIV2161, NIS2161 ESD Protection with Automotive Short-toBattery & Ground Protection Low Capacitance ESD Protection w/ short− to−battery and short−to−ground Protection for Automotive High Speed Data Lines The NIS/NIV2161 is designed to protect high speed data lines from ESD as well as short to vehicle battery situations. The ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines while the low RDS(on) FET limits distortion on the signal lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB and LVDS protocols. Features • Low Capacitance (0.40 pF Typical, I/O to GND) • Protection for the Following Standards: IEC 61000−4−2 (Level 4) & ISO 10605 • Integrated MOSFETs for Short−to−Battery and Short−to−Ground Protection • NIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Automotive High Speed Signal Pairs • USB 2.0/3.0 • LVDS • APIX 2/3 ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ(max) −55 to +150 °C Storage Temperature Range TSTG −55 to +150 °C Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage Lead Temperature Soldering IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) VGS ±10 V TSLD 260 °C ESD ±8 kV ESD ±15 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com WDFN10 CASE 511CA MARKING DIAGRAM V2 MG G V2 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONFIGURATION AND SCHEMATICS 10 9 8 7 6 12345 (Top View) Pin 2 – D+ Host Pin 4 – D−Host Pin 1 and Pin 10 – Source 1 Pin 3 – 5V Pin 3 – 5V Pin 9 – D+ Pin 7 – D− Pin 3 – 5V Pin 3 – 5V Pin 5 and Pin 6 – Source 2 Pin 8 – GND ORDERING INFORMATION Device Package Shipping† NIV2161MTTAG NIS2161MTTAG WDFN10 (Pb−Free) WDFN10 (Pb−Free) 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 1 November, 2018 − Rev. 3 Publication Order Number: NIV2161/D NIV2161, NIS2161 ELECTRICAL CHARACTERISTICS (TA = 25_C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Clamping Voltage Clamping Voltage (Note 1) Clamping Voltage TLP (Note 2) See Figures 5 & 6 Junction Capacitance Match VRWM I/O Pin to GND 16 V VBR IT = 1 mA, I/O Pin to GND 16.5 23 V IR VRWM = 5 V, I/O Pin to GND 1.0 mA VC IPP = 1 A, I/O Pin to GND (8/20 ms pulse) 29 V VC IEC61000−4−2, ±8 KV Contact See Figures 1 & 2 VC IPP = ±8 A IPP = ±16 A 39 V 66 V D CJ VR = 0 V, f = 1 MHz between I/O 1 to GND 1.0 % and I/O 2 to GND Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and 0.40 pF GND (Pin 7 to GND, Pin 9 to GND) Drain−to−Source Breakdown Voltage VBR(DSS) VGS = 0 V, ID = 100 mA 30 V Drain−to−Source Breakdown Voltage Temperature Coefficient VBR(DSS)/ Reference to 25_C, ID = 100 mA TJ 27 mV/_C Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 30 V 1.0 mA Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±5 V ±1.0 mA Gate Threshold Voltage (Note 3) VGS(TH) VDS = VGS, ID = 100 mA 0.1 1.0 1.5 V Gate Threshold Voltage Temperature Coefficient VGS(TH)/ TJ Reference to 25_C, ID = 100 mA −2.5 mV/_C Drain−to−Source On Resistance RDS(on) VGS = 4.5 V, ID = 125 mA 1.4 7.0 W VGS = 2.5 V, ID = 125 mA 2.3 7.5 Forward Transconductance gFS VDS = 3.0 V, ID = 125 mA 80 mS Switching Turn−On Delay Time (Note 4) Switching Turn−On Rise Time (Note 4) td(ON) tr VGS = 4.5 V, VDS = 24 V ID = 125 mA, RG = 10 VW 9 nS 41 nS Switching Turn−Off Delay Time (Note 4) td(OFF) 96 nS Switching Turn−Off Fall Time (Note 4) tf 72 nS Drain−to−Source Forward Diode Voltage VSD VGS = 0 V, Is = 125 mA 0.79 0.9 V 3 dB Bandwidth fBW RL = 50 W 5 GHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For test procedure see Figures 3 and 4 and application no.


NIV2161 NIS2161 NIV6350


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