DatasheetsPDF.com

HJ4060 Dataheets PDF



Part Number HJ4060
Manufacturers Texas Instruments
Logo Texas Instruments
Description 14-Stage Binary Counter
Datasheet HJ4060 DatasheetHJ4060 Datasheet (PDF)

Data sheet acquired from Harris Semiconductor SCHS207G February 1998 - Revised October 2003 CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator [ /Title (CD74 HC406 0, CD74 HCT40 60) /Subject (High Speed CMOS Features • Onboard Oscillator • Common Reset • Negative-Edge Clocking • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads.

  HJ4060   HJ4060


Document
Data sheet acquired from Harris Semiconductor SCHS207G February 1998 - Revised October 2003 CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator [ /Title (CD74 HC406 0, CD74 HCT40 60) /Subject (High Speed CMOS Features • Onboard Oscillator • Common Reset • Negative-Edge Clocking • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of φI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC4060F3A -55 to 125 16 Ld CERDIP CD54HCT4060F3A -55 to 125 16 Ld CERDIP CD74HC4060E -55 to 125 16 Ld PDIP CD74HC4060M -55 to 125 16 Ld SOIC CD74HC4060MT -55 to 125 16 Ld SOIC CD74HC4060M96 -55 to 125 16 Ld SOIC CD74HC4060PW -55 to 125 16 Ld TSSOP CD74HC4060PWR -55 to 125 16 Ld TSSOP CD74HC4060PWT -55 to 125 16 Ld TSSOP CD74HCT4060E -55 to 125 16 Ld PDIP CD74HCT4060M -55 to 125 16 Ld SOIC CD74HCT4060MT -55 to 125 16 Ld SOIC CD74HCT4060M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4060, CD54HCT4060 (CERDIP) CD74HC4060 (PDIP, SOIC, TSSOP) CD74HCT4060 (PDIP, SOIC) TOP VIEW Q12 1 Q13 2 Q14 3 Q6 4 Q5 5 Q7 6 Q4 7 GND 8 16 VCC 15 Q10 14 Q8 13 Q9 12 MR 11 φI 10 φO 9 φO CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 Functional Diagram CD54/74HC4060, CD54/74HCT4060 12 MR 11 φI 14-STAGE RIPPLE COUNTER AND OSCILLATOR 7 Q4 5 Q5 4 Q6 6 Q7 14 Q8 13 Q9 15 Q10 1 Q12 2 Q13 3 Q14 9 φO 10 φO GND = 8 VCC = 16 øO 9 10 øO 11 ø1 12 MR ø1 Q1 FF1 ø1 Q1 R ø4 Q4 FF4 ø4 Q4 R ø5 Q13 FF5 - FF13 ø5 Q13 R ø14 Q14 FF14 ø14 Q14 R 7 2 Q4 5, 4, 6, 14, 13, 15, 1 Q13 Q5 - Q10, Q12 FIGURE 1. LOGIC BLOCK DIAGRAM TRUTH TABLE øI MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs are Low 3 Q14 2 CD54/74HC4060, CD54/74HCT4060 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 108 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..


HC4060M HJ4060 HCT4060M


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)