DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
SN54HC112, SN74HC112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISE...
Description
SN54HC112, SN74HC112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 40-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max
description/ordering information
The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.
SN54HC112 . . . J OR W PACKAGE SN74HC112 . . . D OR N PACKAGE
(TOP VIEW)
1CLK 1 1K 2 1J 3
1PRE 4 1Q 5 1Q 6 2Q 7
GND 8
16 VCC 15 1CLR 14 2CLR 13 2CLK 12 2K 11 2J 10 2PRE 9 2Q
SN54HC112 . . . FK PACKAGE (TOP VIEW)
1K 1CLK NC VCC 1CLR
1J 1PRE
NC 1Q 1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLR 2CLK NC 2K 2J
2Q GND
NC 2Q 2PRE
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE...
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