SN74HC109N

SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features Wide operating voltage range of 2 V to 6 V Low input current of 1 μA max High-current outputs drive up to 10 LSTTL loads Low power consumption, 40-μA max ICC Typical tpd = 12 ns ±4-mA output drive at 5 V 2 Description These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flipflops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. PART NUMBER SN54HC109J SN74HC109D SN74HC109N SN74HC109NS SNJ54HC109FK SNJ54HC109W Device Information PACKAGE(1) BODY SIZE (NOM) CDIP (16) 24.38 mm × 6.92 mm SOIC (16) 9.90 mm × 3.90 mm PDIP (16) 19.31 mm × 6.35 mm SO (16) 6.20 mm × 5.30 mm LCCC (20) 8.89 mm × 8.45 mm CFP (16) 10.16 mm × 6.73 mm (1) For all available ...