SNJ54HC109FK

D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W PACKAGE SN74HC109 . . . D, N, OR NS PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN54HC109, SN74HC109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 D Low Power Consumption, 40-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V SN54HC109 . . . FK PACKAGE (TOP VIEW) 1J 1CLR NC VCC 2CLR 1K 1CLK NC 1PRE 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2K NC 2CLK 2PRE 1Q GND NC 2Q 2Q NC − No internal connection description/ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can p...