SNJ54HC174J

D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Contain Six Flip-Flops With Single-Rail Outputs D Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators description/ordering information These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. SN54HC174, SN74HC174 HEX DĆTYPE FLIPĆFLOPS WITH CLEAR SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003 SN54HC174 . . . J OR W PACKAGE SN74HC174 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) CLR 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7 GND 8 16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 CLK SN54HC174 . . . FK PACKAGE (TOP VIEW) 1Q CLR NC VCC 6Q 3 2 1 20 19 1D 4 18 6D 2D 5 17 5D NC 6 16 NC 2Q 7 15 5Q 3D 8 14 4D 9 10 11 12 13 3Q GND NC CLK 4Q NC − No internal connection ORDERING INFORMATION TA PACKAGE† PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC174N SN74HC174N Tube of 40 SN74HC174D SOIC − D Reel of 25...