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FEATURES
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• Synchronous Parallel Load • Positive-Edge-Triggered Clocking • J and K Inputs to First Stage • Complementary Outputs From Last Stage • Package Options: Plastic and Ceramic DIPS
and Ceramic Chip Carriers • Dependable Texas lnstruments Quality and
Reliability
DESCRIPTION/ORDERING INFORMATION
These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).
Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.
The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.
SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007
SN54HC195 . . . J PACKAGE (TOP VIEW)
CLR 1 J2 K3 A4 B5 C6 D7
GND 8
16 VCC 15 QA 14 QB 13 QC 12 QD 11 QD 10 CLK
9 SH/LD
SN54HC195 . . . FK PACKAGE (TOP VIEW)
J CLR NC VCC QA
K
3 2 1 20 19
4
18
QB
A5
17 QC
NC 6
16 NC
B7
15 QD
C8
14 QD
9 10 11 12 13
D GND
NC SH/LD
CLK
NC − No internal connection
LOGIC SYMBOL†
(1) CLR SH/LD (9)
(10) CLK
(2) J
(3) K
(4) A
(5) B
(6) C
(7) D
SRG4 R M1 (SHIFT) M2 (LOAD)
C3/1
1,3J 1,3K 2,3D 2,3D
(15) QA
(14) QB
(13) QC
(12) QD
(11) QD
† This symbol is in accordance with ANSI/IEEE Std 91−1984 and IEC Publication 617−12.
Pin numbers shown are for J package.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1992–2007, Texas Instruments Incorporated
SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007
(1) CLR CLK (10) SH/LD (9)
LOGIC DIAGRAM (POSITIVE LOGIC)
J (2)
TG
TG
K (3)
TG
TG
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R
(15)
C1
QA
1D
A (4)
(5) B
TG
R
(14)
C1
QB
1D TG
C (6)
TG
R C1 (153) QC
1D TG
D (7) Pin numbers shown are for J package.
TG
R
(12) QD
C1 1D
(11) QD
TG
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Copyright © 1992–2007, Texas Instruments Incorporated
Product Folder Link(s): SN54HC195
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SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007
CLR SH/LD CLK
L
X
X
H
L
↑
H
H
L
H
H
↑
H
H
↑
H
H
↑
H
H
↑
FUNCTION TABLE
INPUTS
SERIAL
PARALLEL
J
K
A
B
C
D
X
X
X
X
X
X
X
X
a
b
c
d
X
X
X
X
X
X
L
H
X
X
X
X
L
L
X
X
X
X
H
H
X
X
X
X
H
L
X
X
X
X
OUTPUTS
QA
L a QA0 QA0 L H Q An
QB
L b QB0 QA0 QAn QAn QAn
QC
L c QC0 QBn QBn QBn QBn
QD Q D
L d QD0 QCn QCn QCn QCn
H d Q D0 Q Cn Q Cn Q Cn Q Cn
CLK
Serial Inputs
CLR J
K
SH/LD A
Parallel
B
Data
Inputs
C
D
QA
QB Outputs
QC
QD
Clear
TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES
H L H L
Serial Shift
Load
Serial Shift
Copyright © 1992–2007, Texas Instruments Incorporated Product Folder Link(s): SN54HC195
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SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
IIK
Input clamp current
VI < 0 or VI > VCC
IOK Output clamp current
VO < 0 or VO > VCC
IO
Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND pins
Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package
Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package
Tstg Storage temperature range
MIN
MAX UNIT
–0.5
7V
±20 mA
±20 mA
25 mA
50 mA
300 °C
260 °C
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VCC Supply voltage VIH High-level input voltage
VIL Low-level input volt.