Octal Inverting Transparent Latch
Data sheet acquired from Harris Semiconductor SCHS187C
January 1998 - Revised July 2003
CD54/74HC533, CD54/74HCT533, CD...
Description
Data sheet acquired from Harris Semiconductor SCHS187C
January 1998 - Revised July 2003
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
[ /Title (CD74H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed
Features
Description
Common Latch-Enable Control
Common Three-State Output Enable Control
Buffered Inputs
Three-State Outputs
Bus Line Driving Capacity
TCyLp=ic1a5l pPFr,oTpAag=a2ti5oonCD(eDlaatya=to13Onustpaut tV) CC = 5V, Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high-speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the da...
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