CD54HCT573

CD54HCT573, CD74HCT573 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 D 4.5-V to 5.5-V VCC Operation D Wide Operating Temperature Range of −55°C to 125°C D Balanced Propagation Delays and Transition Times D Standard Outputs Drive Up To 10 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs D Inputs Are TTL-Voltage Compatible description/ordering information The ’HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. CD54HCT573 . . . F PACKAGE CD74HCT573 . . . DB, E, OR M PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the ...