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D-TYPE LATCHES. CD74HCT573E Datasheet

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D-TYPE LATCHES. CD74HCT573E Datasheet






CD74HCT573E LATCHES. Datasheet pdf. Equivalent




CD74HCT573E LATCHES. Datasheet pdf. Equivalent





Part

CD74HCT573E

Description

OCTAL TRANSPARENT D-TYPE LATCHES



Feature


CD54HCT573, CD74HCT573 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 D 4.5-V to 5.5-V VCC Operatio n D Wide Operating Temperature Range of −55°C to 125°C D Balanced Propagat ion Delays and Transition Times D Stand ard Outputs Drive Up To 10 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs D Input.
Manufacture

Texas Instruments

Datasheet
Download CD74HCT573E Datasheet


Texas Instruments CD74HCT573E

CD74HCT573E; s Are TTL-Voltage Compatible description /ordering information The ’HCT573 dev ices are octal transparent D-type latch es. When the latch-enable (LE) input is high, the Q outputs follow the data (D ) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. CD54HCT573 . . . F PACKAGE CD74HCT573 . . . DB, E, OR M PACKAGE (T OP VIEW) OE 1 1D 2 .


Texas Instruments CD74HCT573E

2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 1 0 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE A buffered ou tput-enable (OE) input can be used to p lace the eight outputs in either a norm al logic state (high or low) or the hig h-impedance state. In the high-impedanc e state, the outputs neither load nor d rive the bus lines significantly. The h igh-impedance stat.


Texas Instruments CD74HCT573E

e and increased drive provide the capabi lity to drive bus lines without interfa ce or pullup components. OE does not a ffect the internal operations of the la tches. Old data can be retained or new data can be entered while the outputs a re in the high-impedance state. To ens ure the high-impedance state during pow er up or power down, OE should be tied to VCC through a p.

Part

CD74HCT573E

Description

OCTAL TRANSPARENT D-TYPE LATCHES



Feature


CD54HCT573, CD74HCT573 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 D 4.5-V to 5.5-V VCC Operatio n D Wide Operating Temperature Range of −55°C to 125°C D Balanced Propagat ion Delays and Transition Times D Stand ard Outputs Drive Up To 10 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs D Input.
Manufacture

Texas Instruments

Datasheet
Download CD74HCT573E Datasheet




 CD74HCT573E
CD54HCT573, CD74HCT573
OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
D 4.5-V to 5.5-V VCC Operation
D Wide Operating Temperature Range of
−55°C to 125°C
D Balanced Propagation Delays and
Transition Times
D Standard Outputs Drive Up To 10 LS-TTL
Loads
D Significant Power Reduction Compared to
LS-TTL Logic ICs
D Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
CD54HCT573 . . . F PACKAGE
CD74HCT573 . . . DB, E, OR M PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 VCC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − E Tube
CD74HCT573E
CD74HCT573E
SSOP − DB Tape and reel CD74HCT573DBR HK573
−55°C to 125°C
SOIC − M
Tube
Tape and reel
CD74HCT573M
CD74HCT573M96
HCT573M
CDIP − F Tube
CD54HCT573F3A CD54HCT573F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 CD74HCT573E
CD54HCT573, CD74HCT573
OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1
OE
LE 11
C1
1D 2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 CD74HCT573E
CD54HCT573, CD74HCT573
OCTAL TRANSPARENT DĆTYPE LATCHES
WITH 3ĆSTATE OUTPUTS
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX
TA = −55°C
TO 125°C
MIN MAX
TA = −40°C
TO 85°C
MIN MAX
UNIT
VCC
VIH
VIL
VI
VO
t/v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition rise or fall rate
4.5 5.5 4.5 5.5 4.5 5.5 V
2
2
2
V
0.8
0.8
0.8 V
VCC
VCC
500
VCC
VCC
500
VCC V
VCC V
500 ns
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN MAX
TA = −55°C
TO 125°C
MIN MAX
TA = −40°C
TO 85°C
MIN MAX
UNIT
VOH
VOL
II
IOZ
ICC
ICC†
VI = VIH or VIL
IOH = −20 µA
IOH = −6 mA
4.4
4.5 V
3.98
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
0.1
4.5 V
0.26
VI = VCC or 0
5.5 V
±0.1
VO = VCC or 0
5.5 V
±0.5
VI = VCC or 0,
IO = 0
5.5 V
8
One input at VCC − 2.1 V, Other inputs at 0 or VCC
4.5 V to
5.5 V
360
4.4
4.4
V
3.7
3.84
0.1
0.1
V
0.4
0.33
±1
±1 µA
±10
±5 µA
160
80 µA
490
450 µA
Ci
10
10
10 pF
Co
20
20
20 pF
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
HCT INPUT LOADING TABLE
INPUT UNIT LOAD
OE
1.25
Any D
0.3
LE
0.65
Unit load is ICC limit
specified in electrical
characteristics table (e.g.,
360 µA max at 25°C).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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