8-Bit Shift Register
Data sheet acquired from Harris Semiconductor SCHS191C
January 1998 - Revised October 2003
CD54HC597, CD74HC597, CD74HC...
Description
Data sheet acquired from Harris Semiconductor SCHS191C
January 1998 - Revised October 2003
CD54HC597, CD74HC597, CD74HCT597
High-Speed CMOS Logic 8-Bit Shift Register with Input Storage
[ /Title (CD74 HC597 , CD74 HCT59 7) /Subject (High Speed CMOS
Features
Description
Buffered Inputs
Asynchronous Parallel Load
Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A “low” on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A “low” master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL is high.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE...
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