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LMC6024 Dataheets PDF



Part Number LMC6024
Manufacturers Texas Instruments
Logo Texas Instruments
Description Low Power CMOS Quad Operational Amplifier
Datasheet LMC6024 DatasheetLMC6024 Datasheet (PDF)

LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 LMC6024 Low Power CMOS Quad Operational Amplifier Check for Samples: LMC6024 FEATURES 1 •2 Specified for 100 kΩ and 5 kΩ Loads • High Voltage Gain 120 dB • Low Offset Voltage Drift 2.5 μV/°C • Ultra Low Input Bias Vurrent 40 fA • Input Common-mode Range Includes V− • Operating Range from +5V to +15V Supply • Low Distortion 0.01% at 1 kHz • Slew Rate 0.11 V/μs • Micropower Operation 1 mW APPLICATIONS • High-impedance Buffer or Pre.

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LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 LMC6024 Low Power CMOS Quad Operational Amplifier Check for Samples: LMC6024 FEATURES 1 •2 Specified for 100 kΩ and 5 kΩ Loads • High Voltage Gain 120 dB • Low Offset Voltage Drift 2.5 μV/°C • Ultra Low Input Bias Vurrent 40 fA • Input Common-mode Range Includes V− • Operating Range from +5V to +15V Supply • Low Distortion 0.01% at 1 kHz • Slew Rate 0.11 V/μs • Micropower Operation 1 mW APPLICATIONS • High-impedance Buffer or Preamplifier • Current-to-voltage Converter • Long-term Integrator • Sample-and-hold Circuit • Peak Detector • Medical Instrumentation • Industrial Controls DESCRIPTION The LMC6024 is a CMOS quad operational amplifier which can operate from either a single supply or dual supplies. Its performance features include an input common-mode range that reaches V−, low input bias current and voltage gain (into 100 kΩ and 5 kΩ loads) that is equal to or better than widely accepted bipolar equivalents, while the power supply requirement is less than 1 mW. This chip is built with Texas Instrument's advanced Double-Poly Silicon-Gate CMOS process. See the LMC6022 datasheet for a CMOS dual operational amplifier with these same features. Connection Diagram Top View Figure 1. 14-Pin DIP and SOIC Package See Package Number D0014A These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1)(2) Differential Input Voltage Supply Voltage (V+ − V−) Lead Temperature Storage Temperature Range Voltage at Output/Input Pin Current at Input Pin Current at Output Pin Current at Power Supply Pin Output Short Circuit to V+ Output Short Circuit to V− Junction Temperature ESD Tolerance(5) Power Dissipation Soldering, 10 sec. ±Supply Voltage 16V 260°C −65°C to +150°C (V+) + 0.3V, (V−) − 0.3V ±5 mA ±18 mA 35 mA See (3) See (4) 150°C 1000V See (6) (1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. (4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversly affect reliability. (5) Human body model, 100 pF discharge through a 1.5 kΩ resistor. (6) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) − TA)/θJA. Operating Ratings Temperature Range Supply Voltage Range Power Dissipation Thermal Resistance (θJA)(2) 14-Pin DIP 14-Pin SOIC −40°C ≤ TJ ≤ +85°C 4.75V to 15.5V See (1) 85°C/W 115°C/W (1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. (2) All numbers apply for packages soldered directly into a PC board. 2 Submit Documentation Feedback Product Folder Links: LMC6024 Copyright © 2000–2013, Texas Instruments Incorporated LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 DC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25°C. Parameter Test Conditions Typical (1) LMC6024I Limit (2) Units VOS Input Offset Voltage 1 9 mV 11 Max ΔVOS/ΔT Input Offset Voltage Average Drift 2.5 μV/°C IB Input Bias Current 0.04 pA 200 Max IOS Input .


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