SN74AUC1G02

www.ti.com SN74AUC1G02 SINGLE 2-INPUT POSITIVE-NOR GATE SCES369P – SEPTEMBER 2001 – REVISED MARCH 2007 FEATURES Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 2.4 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) A 1 B 2 5 VCC A1 B2 5 VCC A1 B2 5 VCC GND 3 4 Y B2 GND 3 4Y A 1 5 VCC GND 3 4Y GND 3 4 Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G02 performs the Boolean function Y = A + B or Y = AB in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devic...